Semiconductor structure and method for reviewing defects

• US 10,082,471 B2
• Filed: 01/02/2017
• Issued: 09/25/2018
• Est. Priority Date: 01/02/2017
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Yung-Teng, Lin, Hung-Chin, Sun, Chia-Chen, Wu, Chih-Yu, Chen, Jun-Ming, Hung, Chung-Chih, Chen, Sheng-Chieh
• Primary Examiner(s): PHAM, HOA Q
• Application Number:
  US15/396,805
• Publication Number:
  US 20180188185A1
• Time in Patent Office: 631 Days
• Field of Search: 356399-401, 3562371-2375, 257620, 257797, 382149, 438401, 438975, 438795, 438 14
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00

Abstract

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Claims

1. A semiconductor structure comprising:

a wafer comprising a plurality of viewing fields defined thereon;

a plurality of dies defined by a scribe line formed in each viewing field;

a plurality of mark patterns formed in the scribe line; and

a plurality of anchor patterns respectively formed in the review fields, the anchor patterns being different from the mark patterns.

2. The semiconductor structure according to claim 1, wherein the viewing fields are defined in a photolithography process and identified by a defect review apparatus.

3. The semiconductor structure according to claim 1, wherein the mark patterns comprise alignment mark patterns.

4. The semiconductor structure according to claim 1, wherein the anchor patterns are formed in the scribe line at a corner of the dies, respectively.

5. The semiconductor structure according to claim 4, wherein the anchor patterns are formed at the corner of the dies located at a corner of the viewing fields.

6. The semiconductor structure according to claim 4, wherein the anchor patterns are formed at the corner of the dies not located at a corner of the viewing fields.

7. The semiconductor structure according to claim 1, wherein the anchor patterns and mark patterns comprise different shapes.

8. The semiconductor structure according to claim 1, wherein the anchor patterns respectively comprise a plurality of sub-patterns arranged therein, and at least a programmed defect is formed in one of the sub-patterns.

9. The semiconductor structure according to claim 8, wherein the sub-patterns comprise semiconductor patterns, metal patterns, or insulating patterns.

10. The semiconductor structure according to claim 8, wherein the programmed defect comprises a gap defect, a short-end defect, or a bridge defect.