Ultra-low power processor-in-memory architecture
First Claim
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1. An apparatus comprising:
- a memory array comprising a plurality of rows and a plurality of columns;
a switch that electrically connects to a particular row of the plurality of rows of the memory array per cycle; and
an energy storage unit that is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
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Abstract
An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
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Citations
3 Claims
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1. An apparatus comprising:
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a memory array comprising a plurality of rows and a plurality of columns; a switch that electrically connects to a particular row of the plurality of rows of the memory array per cycle; and an energy storage unit that is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeNational Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
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Original AssigneeNational Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
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InventorsDeBenedictis, Erik
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Primary Examiner(s)RIZK, SAMIR WADIE
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Application NumberUS15/824,879Publication NumberTime in Patent Office301 DaysField of SearchUS Class CurrentCPC Class CodesG06F 1/32 Means for saving powerG06F 11/10 Adding special bits or symb...G06F 11/1068 in sector programmable memo...
