Memory having a static cache and a dynamic cache

• US 10,083,119 B2
• Filed: 12/14/2017
• Issued: 09/25/2018
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hale, Christopher S., Ratnam, Sampath K., Muchherla, Kishore K.
• Primary Examiner(s): Lane, John A
• Application Number:
  US15/841,601
• Publication Number:
  US 20180107603A1
• Time in Patent Office: 285 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Claims

1. A method of operating memory, comprising:

determining, upon receiving a command to program data to a memory, whether any blocks of memory cells in a portion of the memory configured to operate as a static single level cell (SLC) cache do not have data stored therein;

programming the data received in the command to the portion of the memory configured to operate as a static SLC cache upon determining there is at least one block of memory cells in that portion of the memory that does not have data stored therein; and

programming the data received in the command to a portion of the memory configured to operate as a dynamic SLC cache or multilevel cell (MLC) memory upon determining there are no blocks of memory cells in the portion of the memory configured to operate as a static SLC cache that do not have data stored therein.

2. The method of claim 1, wherein the method includes:

determining, upon determining there are no blocks of memory cells in the portion of the memory configured to operate as a static SLC cache that do not have data stored therein, whether any blocks of memory cells in the portion of the memory configured to operate as a dynamic SLC cache do not have data stored therein; and

programming the data received in the command to the portion of the memory configured to operate as a dynamic SLC cache upon determining there is at least one block of memory cells in the portion of the memory configured to operate as a dynamic SLC cache that does not have data stored therein.

3. The method of claim 2, wherein the method includes programming the data received in the command to the portion of the memory configured to operate as MLC memory upon determining there are no blocks of memory cells in the portion of the memory configured to operate as a dynamic SLC cache that do not have data stored therein.

4. The method of claim 1, wherein determining whether any blocks of memory cells in the portion of the memory configured to operate as a static SLC cache do not have data stored therein includes determining whether any blocks of memory cells in the portion of the memory configured to operate as a static SLC cache are erased blocks.

5. The method of claim 1, wherein the method includes programming the data received in the command to the at least one block of memory cells in the portion of the memory configured to operate as a static SLC cache upon determining there is at least one block of memory cells in that portion of the memory that does not have data stored therein.

6. The method of claim 1, wherein the method includes receiving the command from a host.

7. The method of claim 1, wherein programming the data received in the command to the portion of the memory configured to operate as a static SLC cache includes caching the data received in the command in the portion of the memory configured to operate as a static SLC cache.

8. An apparatus, comprising:

a memory; and

circuitry configured to;

determine, upon receiving a command to program data to a memory, whether any blocks of memory cells in a portion of the memory configured to operate as a static single level cell (SLC) cache do not have data stored therein;

program the data received in the command to the portion of the memory configured to operate as a static SLC cache upon determining there is at least one block of memory cells in the portion of the memory configured to operate as a static SLC cache that does not have data stored therein;

determine, upon determining there are no blocks of memory cells in the portion of the memory configured to operate as a static SLC cache that do not have data stored therein, whether any blocks of memory cells in a portion of the memory configured to operate as a dynamic SLC cache do not have data stored therein;

program the data received in the command to the portion of the memory configured to operate as a dynamic SLC cache upon determining there is at least one block of memory cells in the portion of the memory configured to operate as a dynamic SLC cache that does not have data stored therein; and

program the data received in the command to a portion of the memory configured to operate as multilevel cell (MLC) memory upon determining there are no blocks of memory cells in the portion of the memory configured to operate as a dynamic SLC cache that do not have data stored therein.

9. The apparatus of claim 8, wherein the circuitry is configured to determine whether any blocks of memory cells in the portion of the memory configured to operate as a static SLC cache do not have data stored therein using a tracking table in the circuitry.

10. The apparatus of claim 8, wherein the portion of the memory configured to operate as MLC memory is configured to operate as triple level cell (TLC) memory.

11. The apparatus of claim 8, wherein the portion of the memory configured to operate as a dynamic SLC cache is included within the portion of the memory configured to operate as MLC memory.

12. The apparatus of claim 8, wherein a size of the portion of the memory configured to operate as a static SLC cache is 3 Gigabytes (GB) or less.

13. The apparatus of claim 8, wherein the portion of the memory configured to operate as a static SLC cache, the portion of the memory configured to operate as a dynamic SLC cache, and the portion of the memory configured to operate as MLC memory are part of a single die of the memory.

14. The apparatus of claim 8, wherein the portion of the memory configured to operate as a dynamic SLC cache includes MLC memory cells configured to operate in SLC mode.

15. A method of operating memory, comprising:

determining, upon receiving a command to program data to a memory, whether an entire portion of the memory configured to operate as a static single level cell (SLC) cache has data stored therein;

programming the data received in the command to the portion of the memory configured to operate as a static SLC cache upon determining the entire portion of the memory configured to operate as a static SLC cache does not have data stored therein; and

programming the data received in the command to a portion of the memory configured to operate as a dynamic SLC cache or multilevel cell (MLC) memory upon determining the entire portion of the memory configured to operate as a static SLC cache has data stored therein.

16. The method of claim 15, wherein the method includes:

determining, upon determining the entire portion of the memory configured to operate as a static SLC cache has data stored therein, whether a quantity of program or erase operations performed on the portion of the memory configured to operate as a dynamic SLC cache meets or exceeds a particular quantity of program or erase operations; and

programming the data received in the command to the portion of the memory configured to operate as MLC memory upon determining the quantity of program or erase operations performed on the portion of the memory configured to operate as a dynamic SLC cache meets or exceeds the particular quantity.

17. The method of claim 16, wherein determining whether the quantity of program or erase operations performed on the portion of the memory configured to operate as a dynamic SLC cache meets or exceeds the particular quantity includes:

tracking the quantity of program or erase operations performed on the portion of the memory configured to operate as a dynamic SLC cache; and

comparing the tracked quantity to the particular quantity.

18. The method of claim 16, wherein the method includes:

determining, upon determining the quantity of program or erase operations performed on the portion of the memory configured to operate as a dynamic SLC cache does not meet or exceed the particular quantity of program or erase operations, whether a quantity of blocks in the portion of the memory configured to operate as a dynamic SLC cache having data stored therein meets or exceeds a particular quantity of blocks; and

programming the data received in the command to the portion of the memory configured to operate as MLC memory upon determining the quantity of blocks in the portion of the memory configured to operate as a dynamic SLC cache having data stored therein meets or exceeds the particular quantity of blocks.

19. The method of claim 18, wherein the method includes programming the data received in the command to the portion of the memory configured to operate as a dynamic SLC cache upon determining the quantity of blocks in the portion of the memory configured to operate as a dynamic SLC cache having data stored therein does not meet or exceed the particular quantity of blocks.

20. The method of claim 18, wherein the method includes determining whether the quantity of blocks in the portion of the memory configured to operate as a dynamic SLC cache having data stored therein meets or exceeds the particular quantity of blocks using a tracking table.