Generating and/or employing a descriptor associated with a memory translation table

• US 10,083,131 B2
• Filed: 12/11/2014
• Issued: 09/25/2018
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Ampere Computing LLC
• Original Assignee: Ampere Computing LLC
• Inventors: Inamdar, Tanmay Sunit, Patel, Ravi Rajendra
• Primary Examiner(s): Sain, Gautam
• Application Number:
  US14/566,945
• Publication Number:
  US 20160170910A1
• Time in Patent Office: 1,384 Days
• Field of Search: 711163
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

Various aspects facilitate implementing a memory translation table associated with key-based indexing. A table component is configured for generating a memory translation table and a key component is configured for allocating a key associated with a memory access based on a virtual address and a set of access permissions. A descriptor component is configured for generating a descriptor associated with the memory translation table that comprises at least the set of access permissions and a portion of the key.

Claims

1. A network communication system, comprising:

a processor configured to execute the following computer executable components;

a table component configured for generating a memory translation table associated with a hardware processing device to facilitate communication with at least one hardware communication device;

a key component configured for allocating a key associated with a memory access based on a virtual address, wherein a first portion of the key comprises a set of access permissions, a second portion of the key comprises a first randomly generated number indicative of a bit value that is randomly generated, and third portion of the key comprises an index value associated with an index location for the memory translation table; and

a descriptor component configured for generating a descriptor and for storing the descriptor at the index location for the memory translation table as specified by the key, wherein the descriptor comprises a portion of the key, and wherein the memory translation table is accessed by a hardware memory engine during the communication with the at least one hardware communication device in response to a first determination that a second randomly generated number included in the descriptor corresponds to the first randomly generated number included in the key, and a second determination that the set of access permissions satisfy a defined criterion.

2. The network communication system of claim 1, wherein the memory translation table is associated with a protection domain identifier that correlates a data packet with a memory mapping associated with the virtual address.

3. The network communication system of claim 2, wherein the memory translation table is a unique memory translation table for the protection domain identifier.

4. The network communication system of claim 2, wherein the descriptor further comprises information associated with the memory mapping.

5. The network communication system of claim 1, wherein the first portion of the key and the second portion of the key comprises a first size and the third portion of the key comprises a second size that is different than the first size.

6. The network communication system of claim 1, wherein the portion of the key and the second portion of the key comprise a corresponding size.

7. The network communication system of claim 1, wherein the first portion of the key and the third portion of the key comprise different bit value sizes.

8. The network communication system of claim 1, wherein the descriptor component is further configured for transmitting the descriptor to the hardware memory engine.

9. The network communication system of claim 1, wherein the key component is configured for determining the virtual address and the set of access permissions based on an application that initiates generation of the memory translation table.

10. The network communication system of claim 1, wherein the key component is configured for transmitting the key to the at least one hardware communication device.

11. The network communication system of claim 1, wherein the descriptor component is configured for storing the descriptor at the index location for the memory translation table in response to a determination that a memory space associated with the memory translation table satisfies a defined criterion.

12. A computer implemented method, comprising:

generating a memory translation table associated with a hardware processing device to facilitate communication with at least one hardware communication device;

allocating a key associated with a memory access based on a virtual address, a first randomly generated number indicative of a number value that is randomly generated, and a set of access permissions;

generating a descriptor for the memory translation table, comprising storing the descriptor at an index location for the memory translation table as specified by the key, the descriptor comprising at least the set of access permissions and a portion of the key; and

providing the memory translation table to a hardware memory engine during the communication with the at least one hardware communication device in response to a first determination that a second randomly generated number included in the descriptor corresponds to the first randomly generated number included in the key, and a second determination that the set of access permissions satisfy a defined criterion.

13. The computer implemented method of claim 12, further comprising storing the descriptor in response to a determination that a memory space associated with the memory translation table satisfies a defined criterion.

14. The computer implemented method of claim 12, further comprising associating the memory translation table with a protection domain identifier that correlates a data packet with a memory mapping associated with the virtual address.

15. The computer implemented method of claim 12, wherein the generating the descriptor comprises storing a memory region length in the descriptor.

16. The computer implemented method of claim 12, wherein the generating the descriptor comprises storing the first randomly generated number associated with the key in the descriptor.

17. The computer implemented method of claim 12, wherein the generating the descriptor comprises storing an index associated with the memory translation table in the descriptor.

18. A computer implemented method, comprising:

receiving, by a hardware memory engine, a descriptor stored at an index location for a memory translation table as specified by a key;

validating, by the hardware memory engine, at least a randomly generated number included in the descriptor by comparing the randomly generated number included in the descriptor with another randomly generated number included in the key that is indicative of a bit value that is randomly generated; and

initiating, by the hardware memory engine, memory translation with respect to data associated with a processor in response to at least a valid randomly generated number and a determination that a set of access permissions included in the descriptor satisfy a defined criterion.

19. The computer implemented method of claim 18, wherein

the validating comprises validating the set of access permission included in the descriptor.

20. The computer implemented method of claim 18, wherein

the validating comprises validating a memory region length included in the descriptor, and

the initiating comprises initiating the memory translation in response to a valid memory region length.