Target optimization method for improving lithography printability
First Claim
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1. A method comprising:
- receiving an IC design layout for a target pattern given ideal processing conditions, wherein the target pattern includes a target feature having a target contour;
modifying the target contour of the target feature to compensate for processing conditions that cause a fabricated pattern to vary from the target pattern;
generating an optimized target pattern when the modified target contour of the target feature achieves functionality of the target pattern as defined by a constraint layer, wherein the constraint layer defines a portion of the target pattern that constrains the modified contour of the target feature; and
fabricating a mask based on the optimized target pattern.
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Abstract
Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.
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Citations
20 Claims
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1. A method comprising:
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receiving an IC design layout for a target pattern given ideal processing conditions, wherein the target pattern includes a target feature having a target contour; modifying the target contour of the target feature to compensate for processing conditions that cause a fabricated pattern to vary from the target pattern; generating an optimized target pattern when the modified target contour of the target feature achieves functionality of the target pattern as defined by a constraint layer, wherein the constraint layer defines a portion of the target pattern that constrains the modified contour of the target feature; and fabricating a mask based on the optimized target pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving an IC design layout for a target pattern given ideal processing conditions; defining a constraint layer based on a functionality of the target pattern, wherein the constraint layer defines a portion of the target pattern that constrains a contour of a target feature of the target pattern when modified to compensate for processing conditions that cause a fabricated pattern to vary from the target pattern; defining a cost function that correlates a spatial relationship between the contour of the target feature and the constraint layer; modifying a target contour of the target feature using the constraint layer and the cost function; generating an optimized target pattern when the modified target contour of the target feature minimizes the cost function; and fabricating a mask based on the optimized target pattern. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method comprising:
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defining a constraint layer for a first pattern layer that corresponds with a target pattern defined by an integrated circuit (IC) layout, wherein the constraint layer constrains a contour of a target feature of the first pattern layer based on a second pattern layer that corresponds with the target pattern; iteratively modifying a contour of the target feature until a simulated fabricated pattern functions substantially similar to the target pattern, thereby generating an optimized first pattern layer that includes the target feature having the modified target contour; and generating a mask based on the optimized first pattern layer. - View Dependent Claims (18, 19, 20)
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Specification