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Ring oscillator built from SRAM cells interconnected via standard cell-interface

  • US 10,083,740 B2
  • Filed: 06/18/2017
  • Issued: 09/25/2018
  • Est. Priority Date: 06/21/2016
  • Status: Active Grant
First Claim
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1. An Integrated Circuit (IC), comprising:

  • a memory comprising multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers;

    circuit interconnections, fabricated in one or more second layers separate from the first layers, the circuit interconnections configured to interconnect a subgroup of the standard-library SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and

    control logic, coupled to the cell-interfaces via the circuit interconnections, the control logic being configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator, wherein a frequency of the oscillation is indicative of a speed of the SRAM cells of the memory.

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