Ring oscillator built from SRAM cells interconnected via standard cell-interface

• US 10,083,740 B2
• Filed: 06/18/2017
• Issued: 09/25/2018
• Est. Priority Date: 06/21/2016
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Ecker, Reuven
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/626,133
• Publication Number:
  US 20170365332A1
• Time in Patent Office: 464 Days
• Field of Search: 365 72, 365154, 365156
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.

Claims

1. An Integrated Circuit (IC), comprising:

a memory comprising multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers;

circuit interconnections, fabricated in one or more second layers separate from the first layers, the circuit interconnections configured to interconnect a subgroup of the standard-library SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and

control logic, coupled to the cell-interfaces via the circuit interconnections, the control logic being configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator, wherein a frequency of the oscillation is indicative of a speed of the SRAM cells of the memory.

2. The IC according to claim 1, wherein all the circuit interconnections among the SRAM cells of the subgroup, for forming the ring oscillator, are made without altering a topology of the standard-library SRAM cells disposed in the first layers.

3. The IC according to claim 1, wherein the SRAM cells comprise eight-transistor (8T) SRAM cells, ones of the 8T SRAM cells having a storage capacity of a single bit, and wherein the 8T SRAM cells comprise decoupled writing and reading circuits, the decoupled writing and reading circuits being connected to respective ports of the cell-interface.

4. The IC according to claim 1, wherein the cell-interface comprises a Bit Line port and a Bit Line Bar (BLB) port for writing a bit value into the SRAM cell, and a Read Bit Line (RBL) port for reading the bit value stored in the SRAM cell, and wherein the circuit interconnections used in forming the ring oscillator interconnect the RBL port of the SRAM cell in each stage in the cascade, excluding the last stage, to the BLB port of the SRAM cell in a subsequent stage in the cascade, and interconnect the RBL port of the SRAM cell in the last stage in the cascade to the BLB port of the SRAM cell in the first stage in the cascade.

5. The IC according to claim 4, wherein the control logic is configured to apply to the cell-interfaces an enable signal that causes an enabled SRAM cell to assume a respective bit value in response to a logic level present at its respective BLB port.

6. The IC according to claim 4, wherein the control logic is configured to trigger the oscillation by temporarily pulling down a voltage level at the BLB port of the SRAM cell in the first stage of the cascade, resulting in storing a bit value in the SRAM cell of the first stage of the cascade, the bit value is propagated via the interconnections of the second layers to subsequent stages of the cascade.

7. The IC according to claim 4, wherein the RBL port of the SRAM cell in a given stage is configured to flip a polarity, in response to a polarity change at the BLB port of the given stage, and to flip the polarity of the RBL port back, in response to a feedback signal from a stage that is M stages cyclically away from the given stage in the cascade, wherein 1<

M<

N.

8. The IC according to claim 7, wherein the feedback signal is configured to pull down the BL port of the given SRAM cell using a pulldown transistor.

9. The IC according to claim 7, wherein a duty cycle of the oscillation of the ring oscillator depends on a ratio between M and N.

10. The IC according to claim 1, wherein the cell-interface comprises multiple cell-interface ports, and wherein each of the N stages in the cascade comprises two or more SRAM cells whose respective cell-interface ports are connected in parallel using the circuit interconnections.

11. A method, comprising:

applying an input signal to a ring oscillator comprising a subgroup of multiple standard-library Static Random Access Memory (SRAM) cells of a memory, disposed on a substrate of an Integrated Circuit (IC) in multiple first layers, wherein circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect the cell-interfaces of the subgroup of the SRAM cells to form the ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and

estimating a speed of the SRAM cells of the memory by measuring a frequency of oscillation of the ring oscillator that is initiated by the input signal.

12. The method according to claim 11, and comprising applying to the cell-interfaces an enable signal that causes an enabled SRAM cell to assume a respective bit value in response to a logic level present at its respective BLB port.

13. The method to claim 11, wherein triggering the oscillation comprises temporarily pulling down a voltage level at the BLB port of the SRAM cell in the first stage of the cascade, resulting in storing a bit value in the SRAM cell of the first stage of the cascade, the bit value is propagated via the interconnections of the second layers to subsequent stages of the cascade.

14. A method for producing an Integrated Circuit (IC), comprising:

disposing multiple standard-library Static Random Access Memory (SRAM) cells on a substrate of the IC in multiple first layers;

fabricating interconnections in one or more second layers of the IC, separate from the first layers, and interconnecting the cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and

coupling control logic fabricated in the first layers to the cell-interfaces of the SRAM cells in the subgroup via the circuit interconnections of the second layers, wherein the control logic is designed to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator.

15. The method according to claim 14, wherein interconnecting the cell-interfaces comprises interconnecting all of the SRAM cells of the subgroup for forming the ring oscillator without altering a topology of the standard-library SRAM cells disposed in the first layers.

16. The method according to claim 14, wherein disposing the SRAM cells comprises disposing eight-transistor (8T) SRAM cells, ones of the 8T SRAM cells having a storage capacity of a single bit, wherein the 8T SRAM cells comprise decoupled writing and reading circuits, the decoupled writing and reading circuits being connected to respective ports of the cell-interface.