Ring oscillator built from SRAM cells interconnected via standard cell-interface
First Claim
1. An Integrated Circuit (IC), comprising:
- a memory comprising multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers;
circuit interconnections, fabricated in one or more second layers separate from the first layers, the circuit interconnections configured to interconnect a subgroup of the standard-library SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and
control logic, coupled to the cell-interfaces via the circuit interconnections, the control logic being configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator, wherein a frequency of the oscillation is indicative of a speed of the SRAM cells of the memory.
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Accused Products
Abstract
An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.
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Citations
16 Claims
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1. An Integrated Circuit (IC), comprising:
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a memory comprising multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers; circuit interconnections, fabricated in one or more second layers separate from the first layers, the circuit interconnections configured to interconnect a subgroup of the standard-library SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and control logic, coupled to the cell-interfaces via the circuit interconnections, the control logic being configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator, wherein a frequency of the oscillation is indicative of a speed of the SRAM cells of the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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applying an input signal to a ring oscillator comprising a subgroup of multiple standard-library Static Random Access Memory (SRAM) cells of a memory, disposed on a substrate of an Integrated Circuit (IC) in multiple first layers, wherein circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect the cell-interfaces of the subgroup of the SRAM cells to form the ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and estimating a speed of the SRAM cells of the memory by measuring a frequency of oscillation of the ring oscillator that is initiated by the input signal. - View Dependent Claims (12, 13)
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14. A method for producing an Integrated Circuit (IC), comprising:
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disposing multiple standard-library Static Random Access Memory (SRAM) cells on a substrate of the IC in multiple first layers; fabricating interconnections in one or more second layers of the IC, separate from the first layers, and interconnecting the cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that comprises a cascade of N stages defined by the interconnected SRAM cells, wherein access both to the SRAM cells that form the ring oscillator, and to the other SRAM cells in the memory, is performed only via identical, unmodified, standard-cell cell-interfaces of the standard-library SRAM cells; and coupling control logic fabricated in the first layers to the cell-interfaces of the SRAM cells in the subgroup via the circuit interconnections of the second layers, wherein the control logic is designed to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator. - View Dependent Claims (15, 16)
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Specification