Semiconductor display device

• US 10,083,995 B2
• Filed: 05/18/2017
• Issued: 09/25/2018
• Est. Priority Date: 04/09/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Murakami, Satoshi, Hayakawa, Masahiko, Kato, Kiyoshi, Osame, Mitsuaki
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/598,651
• Publication Number:
  US 20170256570A1
• Time in Patent Office: 495 Days
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H10K 50/84 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/873 Encapsulations

Abstract

It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

Claims

1. A semiconductor display device comprising:

a pixel portion comprising;

a transistor comprising;

an active layer over a substrate; and

a gate electrode over the active layer with a gate insulating layer interposed therebetween;

a first inorganic insulating layer over and in direct contact with the gate electrode and the gate insulating layer;

an organic layer over the first inorganic insulating layer, the organic layer including a first opening part;

a contact hole in the gate insulating layer and the first inorganic insulating layer,

wherein the first opening part and the contact hole overlap each other,

wherein a wiring is over the organic layer, the wiring is in direct contact with the active layer through the first opening part and the contact hole,

wherein the wiring includes a first layer containing titanium, a second layer containing aluminum, and a third layer containing titanium,

wherein the second layer is between the first layer and the third layer,

wherein a thickness of the second layer is higher than each of a thickness of the first layer and a thickness of the third layer,

wherein the first inorganic insulating layer contains silicon and nitrogen, and

wherein a curvature radius of a part of a surface of the organic layer becomes longer continuously as the organic layer separates from the first opening part.

2. A semiconductor display device according to claim 1, further comprising:

a semiconductor circuit generating a signal for displaying an image on the pixel portion, the semiconductor circuit having a capacitor;

a second inorganic insulating layer covering the organic layer;

wherein the semiconductor circuit comprises a transistor, and the transistor has an active layer, a gate electrode adjacent to the active layer with a gate insulating layer interposed therebetween,

wherein the organic layer having a second opening part,

wherein the first and second inorganic insulating layers are in direct contact with each other in the first opening part and the second opening part, and

wherein the capacitor has a first electrode formed from the same conductive layer as the gate electrode, a second electrode formed from the same conductive layer as the wiring, and a part of the first and second inorganic insulating layers which overlap the first electrode and the second electrode in the second opening part.

3. A semiconductor display device according to claim 1, wherein the organic layer is a positive photosensitive organic layer.

4. A semiconductor display device according to claim 2, wherein the semiconductor circuit is one of a booster circuit, a D/A conversion circuit of a capacity dividing type, a DRAM, an analog latch circuit, or a protective circuit.

5. A semiconductor display device according to claim 1, wherein the organic layer is acrylic.

6. A semiconductor display device according to claim 2, wherein the organic layer inclines at 30°

or more and 65°

or less with respect to the substrate on a tangent line thereof at the end of the first and second opening parts.

7. A semiconductor display device comprising:

a pixel portion comprising;

a transistor comprising;

an active layer over a substrate; and

a gate electrode over the active layer with a gate insulating layer interposed therebetween;

a first inorganic insulating layer over and in direct contact with the gate electrode and the gate insulating layer;

an organic layer over the first inorganic insulating layer, the organic layer including a first opening part;

a contact hole in the gate insulating layer and the first inorganic insulating layer,

wherein the first opening part and the contact hole overlap each other,

wherein a wiring is over the organic layer, the wiring is in direct contact with the active layer through the first opening part and the contact hole,

wherein the wiring includes a first layer containing titanium, a second layer containing aluminum, and a third layer containing titanium,

wherein the second layer is between the first layer and the third layer,

wherein a thickness of the second layer is higher than each of a thickness of the first layer and a thickness of the third layer,

wherein the first inorganic insulating layer contains silicon and nitrogen, and

wherein a sectional shape of a part of a surface of the organic layer at an end of the first opening part draws a parabola having a principal axis within a surface parallel with the substrate.

8. A semiconductor display device according to claim 7, further comprising:

a semiconductor circuit generating a signal for displaying an image on the pixel portion, the semiconductor circuit having a capacitor;

a second inorganic insulating layer covering the organic layer;

wherein the semiconductor circuit comprises a transistor, and the transistor has an active layer, a gate electrode adjacent to the active layer with a gate insulating layer interposed therebetween,

wherein the organic layer having a second opening part,

wherein the first and second inorganic insulating layers are in direct contact with each other in the first opening part and the second opening part, and

wherein the capacitor has a first electrode formed from the same conductive layer as the gate electrode, a second electrode formed from the same conductive layer as the wiring, and a part of the first and second inorganic insulating layers which overlap the first electrode and the second electrode in the second opening part.

9. A semiconductor display device according to claim 7, wherein the organic layer is a positive photosensitive organic layer.

10. A semiconductor display device according to claim 8, wherein the semiconductor circuit is one of a booster circuit, a D/A conversion circuit of a capacity dividing type, a DRAM, an analog latch circuit, or a protective circuit.

11. A semiconductor display device according to claim 7, wherein the organic layer is acrylic.

12. A semiconductor display device according to claim 8, wherein the organic layer inclines at 30°

or more and 65°

or less with respect to the substrate on a tangent line thereof at the end of the first and second opening parts.