Semiconductor device

• US 10,083,996 B2
• Filed: 06/04/2015
• Issued: 09/25/2018
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Tran, Tran
• Application Number:
  US14/730,436
• Publication Number:
  US 20150270295A1
• Time in Patent Office: 1,209 Days
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Claims

1. A semiconductor device comprising:

an insulating layer; and

a transistor comprising;

a source electrode and a drain electrode over the insulating layer;

an oxide layer over and in direct contact with a top portion and an inner side edge of the source electrode and with a top portion and an inner side edge of the drain electrode;

a gate insulating layer over and in direct contact with the oxide layer; and

a gate electrode over and in direct contact with the gate insulating layer,

wherein the oxide layer covers the inner side edge of the source electrode and the inner side edge of the drain electrode, and

wherein the oxide layer covers an outer side edge of at least one of the source electrode and the drain electrode.

4. The semiconductor device according to claim 1,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with the insulating layer in a region not comprised between the source electrode and the drain electrode.

7. The semiconductor device according to claim 1,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with two opposite side edges of one of the source electrode and the drain electrode.

10. The semiconductor device according to claim 1,

wherein the inner side edge of the source electrode faces the inner side edge of the drain electrode, and

wherein the oxide layer extends beyond an outer side edge of the other of the source electrode and the drain electrode that is opposite to the inner side edge of the other of the source electrode and the drain electrode.

13. The semiconductor device according to claim 1,

wherein a top surface of the oxide layer comprises a step in response to a side edge of the source electrode.

16. The semiconductor device according to claim 1,

wherein the oxide layer is an oxide semiconductor layer.

19. The semiconductor device according to claim 1,

wherein the oxide layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

22. The semiconductor device according to claim 1,

wherein the oxide layer comprises indium, gallium, and zinc.

2. A semiconductor device comprising:

an insulating layer;

a transistor comprising;

a source electrode and a drain electrode over the insulating layer;

an oxide layer over and in direct contact with a top portion and an inner side edge of the source electrode and with a top portion and an inner side edge of the drain electrode;

a gate insulating layer over and in direct contact with the oxide layer; and

a gate electrode over and in direct contact with the gate insulating layer,

wherein the oxide layer covers the inner side edge of the source electrode and the inner side edge of the drain electrode, and

a capacitor comprising;

a first electrode and a second electrode facing each other, one of the first electrode and the second electrode being in electrical contact with one of the source electrode and the drain electrode.

5. The semiconductor device according to claim 2,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with the insulating layer in a region not comprised between the source electrode and the drain electrode.

8. The semiconductor device according to claim 2,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with two opposite side edges of one of the source electrode and the drain electrode.

11. The semiconductor device according to claim 2,

wherein the inner side edge of the source electrode faces the inner side edge of the drain electrode, and

wherein the oxide layer extends beyond an outer side edge of one of the source electrode and the drain electrode that is opposite to the inner side edge of the one of the source electrode and the drain electrode.

14. The semiconductor device according to claim 2,

wherein a top surface of the oxide layer comprises a step in response to a side edge of the source electrode.

17. The semiconductor device according to claim 2,

wherein the oxide layer is an oxide semiconductor layer.

20. The semiconductor device according to claim 2,

wherein the oxide layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

23. The semiconductor device according to claim 2,

wherein the oxide layer comprises indium, gallium, and zinc.

3. A semiconductor device comprising:

an insulating layer;

a transistor comprising;

a source electrode and a drain electrode over the insulating layer;

an oxide layer over and in direct contact with a top portion and an inner side edge of the source electrode and with a top portion and an inner side edge of the drain electrode;

a gate insulating layer over and in direct contact with the oxide layer; and

a gate electrode over and in direct contact with the gate insulating layer,

wherein the oxide layer covers the inner side edge of the source electrode and the inner side edge of the drain electrode, and

a capacitor comprising;

a first electrode and a second electrode facing each other, one of the first electrode and the second electrode being an extension of a conductive layer forming one of the source electrode and the drain electrode; and

the oxide layer and the gate insulating layer each between the first electrode and the second electrode.

6. The semiconductor device according to claim 3,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with the insulating layer in a region not comprised between the source electrode and the drain electrode.

9. The semiconductor device according to claim 3,

wherein a cross-section view of the semiconductor device taken along a channel length direction of the transistor shows that the oxide layer is in direct contact with two opposite side edges of one of the source electrode and the drain electrode.

12. The semiconductor device according to claim 3,

wherein the inner side edge of the source electrode faces the inner side edge of the drain electrode, and

wherein the oxide layer extends beyond an outer side edge of one of the source electrode and the drain electrode that is opposite to the inner side edge of the one of the source electrode and the drain electrode.

15. The semiconductor device according to claim 3,

wherein a top surface of the oxide layer comprises a step in response to a side edge of the source electrode.

18. The semiconductor device according to claim 3,

wherein the oxide layer is an oxide semiconductor layer.

21. The semiconductor device according to claim 3,

wherein the oxide layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

24. The semiconductor device according to claim 3,

wherein the oxide layer comprises indium, gallium, and zinc.