MOSFET active area and edge termination area charge balance

• US 10,084,037 B2
• Filed: 10/31/2016
• Issued: 09/25/2018
• Est. Priority Date: 10/05/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Chen, Qufei, Terrill, Kyle, Shi, Sharon
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US15/339,678
• Publication Number:
  US 20170117354A1
• Time in Patent Office: 694 Days
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

Claims

1. A semiconductor device, comprising:

an active area, comprising;

a plurality of active area trenches;

a source region adjacent one or more sidewalls of said plurality of active area trenches;

a gate region located adjacent to and vertically underneath said source region; and

a drain region located adjacent to and vertically underneath said gate region;

and

an edge termination area, comprising;

a gate pickup trench; and

a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area and causes said implants made at the bottom of said trenches formed in said active area to reach a predetermined concentration.

2. The device of claim 1 further comprising:

a layer of oxide formed in said plurality of active area trenches; and

a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

3. The device of claim 2 further comprising:

a plurality of edge termination contacts in said edge termination area.

4. The device of claim 1 wherein said first and said second plurality of implants results in a simultaneous charge balance within said active area and within said edge termination area.

5. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

6. The device of claim 1 wherein said layer of oxide formed in said active area trenches and said edge termination area trenches are formed using a low thermal oxide (LTO) process.

7. The device of claim 1 wherein said active area trenches and said edge termination area trenches are filled with doped polycrystalline.

8. The device of claim 1 wherein said source is formed over a body well comprising a voltage adjustment implant.

9. The device of claim 1 further comprising planar contacts and trench contacts that are filled with metal.

14. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

20. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

10. A semiconductor device, comprising:

an active area, comprising;

a plurality of active area trenches;

a source region adjacent one or more sidewalls of said plurality of active area trenches;

a gate region located adjacent to and vertically underneath said source region; and

a drain region located adjacent to and vertically underneath said gate region;

and

an edge termination area, comprising;

a gate pickup trench; and

a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area.

11. The device of claim 10 further comprising:

a layer of oxide formed in said plurality of active area trenches; and

a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

12. The device of claim 11 further comprising:

a plurality of edge termination contacts in said edge termination area.

13. The device of claim 10 wherein said first and said second plurality of implants results in a simultaneous charge balance within said active area and within said edge termination area.

15. A semiconductor device, comprising:

an active area, comprising;

a plurality of active area trenches;

and

an edge termination area, comprising;

a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area.

16. The device of claim 15 further comprising:

a layer of oxide formed in said plurality of active area trenches; and

a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

17. The device of claim 15 wherein said active area trenches and said edge termination area trenches are filled with doped polycrystalline.

18. The device of claim 15 further comprising a source formed over a body well comprising a voltage adjustment implant.

19. The device of claim 15 further comprising planar contacts and trench contacts that are filled with metal.