Semiconductor device including a superlattice and replacement metal gate structure and related methods
First Claim
1. A semiconductor device comprising:
- a substrate having a channel recess therein;
a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;
source and drain regions spaced apart in the substrate and between a pair of the STI regions; and
a superlattice channel in the channel recess of said substrate extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a replacement gate over the superlattice channel having lateral edges vertically aligned with lateral edges of the superlattice channel.
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Accused Products
Abstract
A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
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Citations
22 Claims
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1. A semiconductor device comprising:
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a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; and a superlattice channel in the channel recess of said substrate extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and a replacement gate over the superlattice channel having lateral edges vertically aligned with lateral edges of the superlattice channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
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a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer, the replacement gate having lateral edges vertically aligned with lateral edges of the superlattice channel. - View Dependent Claims (11, 12, 13)
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14. A semiconductor device comprising:
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a substrate; a pair of spaced apart isolation regions in said substrate; source and drain regions spaced apart in the substrate and between the pair of the isolation regions; the substrate having a channel recess extending between the source and drain regions; a superlattice channel in the channel recess and contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and a gate over the superlattice channel comprising a dielectric layer and a metal gate electrode thereon, the gate having lateral edges vertically aligned with lateral edges of the superlattice channel. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification