FinFET with epitaxial source and drain regions and dielectric isolated channel region
First Claim
1. A method comprising:
- providing at least one fin structure over a stacked structure of an insulator layer that is present over at least one semiconductor layer;
providing a gate structure on a channel region portion of the at least one fin structure;
removing exposed portions of the at least one fin structure;
forming a sacrificial spacer on a sidewall of the gate structure;
removing exposed portions of the insulator layer to provide a pedestal of insulating material exposing a portion of at least one semiconductor layer;
forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer, the first epitaxial material layer contacting the sacrificial spacer;
removing the sacrificial spacer; and
forming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer to provide source and drain regions.
1 Assignment
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Accused Products
Abstract
A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
12 Citations
20 Claims
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1. A method comprising:
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providing at least one fin structure over a stacked structure of an insulator layer that is present over at least one semiconductor layer; providing a gate structure on a channel region portion of the at least one fin structure; removing exposed portions of the at least one fin structure; forming a sacrificial spacer on a sidewall of the gate structure; removing exposed portions of the insulator layer to provide a pedestal of insulating material exposing a portion of at least one semiconductor layer; forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer, the first epitaxial material layer contacting the sacrificial spacer; removing the sacrificial spacer; and forming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer to provide source and drain regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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providing a gate structure on a channel region portion of at least one fin structure, wherein the at least one fin structure is present overlying a stacked structure including an insulating layer overlying a semiconductor layer; removing end portions of the at least one fin structure; removing exposed portions of the insulator layer to provide a pedestal of insulating material; forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer; and forming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer to provide source and drain regions. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification