Semiconductor device comprising power gating device
First Claim
1. A semiconductor device comprising:
- a signal processing circuit, a cache memory, and an input/output interface electrically connected to a bus line;
an address monitoring circuit monitoring whether the signal processing circuit, the cache memory, and the input/output interface are in an access state or not;
first to third switches electrically connected to the signal processing circuit, the cache memory, and the input/output interface, respectively, and configured to select whether to supply power to the signal processing circuit, the cache memory, and the input/output interface in response to a power gating control signal;
a power control circuit outputting the power gating control signal in accordance with a state of the signal processing circuit, a state of the cache memory, and a state of the input/output interface which are monitored by the address monitoring circuit;
a node electrically connected to one of the first to third switches and one of the signal processing circuit, the cache memory, and the input/output interface;
a transistor including an oxide semiconductor film as a semiconductor layer; and
a capacitor electrically connected to the node through a source and a drain of the transistor,wherein the capacitor is electrically connected to the one of the signal processing circuit, the cache memory, and the input/output interface through the node.
1 Assignment
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Accused Products
Abstract
Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state.
120 Citations
17 Claims
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1. A semiconductor device comprising:
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a signal processing circuit, a cache memory, and an input/output interface electrically connected to a bus line; an address monitoring circuit monitoring whether the signal processing circuit, the cache memory, and the input/output interface are in an access state or not; first to third switches electrically connected to the signal processing circuit, the cache memory, and the input/output interface, respectively, and configured to select whether to supply power to the signal processing circuit, the cache memory, and the input/output interface in response to a power gating control signal; a power control circuit outputting the power gating control signal in accordance with a state of the signal processing circuit, a state of the cache memory, and a state of the input/output interface which are monitored by the address monitoring circuit; a node electrically connected to one of the first to third switches and one of the signal processing circuit, the cache memory, and the input/output interface; a transistor including an oxide semiconductor film as a semiconductor layer; and a capacitor electrically connected to the node through a source and a drain of the transistor, wherein the capacitor is electrically connected to the one of the signal processing circuit, the cache memory, and the input/output interface through the node. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a bus line; a signal processing circuit; a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line; an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line; an address monitoring circuit acquiring the first address signal and the second address signal; a power control circuit performing power gating on the cache memory and the input/output interface; a power supply circuit electrically connected to the cache memory through a first node and electrically connected to the input/output interface through a second node; a first transistor including a first oxide semiconductor film as a semiconductor layer; a second transistor including a second oxide semiconductor film as a semiconductor layer; a first capacitor electrically connected to the first node through a source and a drain of the first transistor; and a second capacitor electrically connected to the second node through a source and a drain of the second transistor, wherein switching of the first and second transistors is controlled by the power control circuit, wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal, wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal, wherein the first capacitor is electrically connected to the cache memory through the first node, and wherein the second capacitor is electrically connected to the input/output interface through the second node. - View Dependent Claims (7, 8, 9)
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10. A semiconductor device comprising:
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a bus line; a signal processing circuit; a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line; an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line; a sub-signal processing circuit configured to be booted up by the signal processing circuit; an address monitoring circuit acquiring the first address signal and the second address signal; a power control circuit performing power gating on the signal processing circuit, the cache memory, and the input/output interface; a power supply circuit electrically connected to the signal processing circuit through a first node, electrically connected to the cache memory through a second node, and electrically connected to the input/output interface through a third node; a first transistor including a first oxide semiconductor film as a semiconductor layer; a second transistor including a second oxide semiconductor film as a semiconductor layer; a third transistor including a third oxide semiconductor film as a semiconductor layer; a first capacitor electrically connected to the first node through a source and a drain of the first transistor; a second capacitor electrically connected to the second node through a source and a drain of the second transistor; and a third capacitor electrically connected to the third node through a source and a drain of the third transistor, wherein switching of the first to third transistors is controlled by the power control circuit, wherein the power control circuit is configured to select whether power gating of the signal processing circuit is performed or not according to whether the sub-signal processing circuit is booted up or not, wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal, wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal, wherein the first capacitor is electrically connected to the signal processing circuit through the first node, wherein the second capacitor is electrically connected to the cache memory through the second node, and wherein the third capacitor is electrically connected to the input/output interface through the third node. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification