Semiconductor device comprising power gating device

• US 10,088,886 B2
• Filed: 01/10/2014
• Issued: 10/02/2018
• Est. Priority Date: 01/24/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tamura, Hikaru
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): DeRose, Volvick
• Application Number:
  US14/151,880
• Publication Number:
  US 20140208142A1
• Time in Patent Office: 1,726 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state.

Claims

1. A semiconductor device comprising:

a signal processing circuit, a cache memory, and an input/output interface electrically connected to a bus line;

an address monitoring circuit monitoring whether the signal processing circuit, the cache memory, and the input/output interface are in an access state or not;

first to third switches electrically connected to the signal processing circuit, the cache memory, and the input/output interface, respectively, and configured to select whether to supply power to the signal processing circuit, the cache memory, and the input/output interface in response to a power gating control signal;

a power control circuit outputting the power gating control signal in accordance with a state of the signal processing circuit, a state of the cache memory, and a state of the input/output interface which are monitored by the address monitoring circuit;

a node electrically connected to one of the first to third switches and one of the signal processing circuit, the cache memory, and the input/output interface;

a transistor including an oxide semiconductor film as a semiconductor layer; and

a capacitor electrically connected to the node through a source and a drain of the transistor,

wherein the capacitor is electrically connected to the one of the signal processing circuit, the cache memory, and the input/output interface through the node.

2. The semiconductor device according to claim 1, further comprising first to third logic circuits being electrically connected to the signal processing circuit, the cache memory, and the input/output interface, respectively, and configured to select whether to supply a clock signal to the signal processing circuit, the cache memory, and the input/output interface in response to a clock gating control signal,

wherein the power control circuit is configured to output the clock gating control signal in accordance with the state of the signal processing circuit, the state of the cache memory, and the state of the input/output interface.

3. The semiconductor device according to claim 2, wherein the clock gating control signal is input to a gate of the transistor.

4. The semiconductor device according to claim 2, wherein the clock gating control signal stops supply of the clock signal before the power gating control signal is switched to stop supply of the power.

5. The semiconductor device according to claim 2, wherein the clock gating control signal restarts supply of the clock signal after the power gating control signal is switched to restart supply of the power.

6. A semiconductor device comprising:

a bus line;

a signal processing circuit;

a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line;

an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line;

an address monitoring circuit acquiring the first address signal and the second address signal;

a power control circuit performing power gating on the cache memory and the input/output interface;

a power supply circuit electrically connected to the cache memory through a first node and electrically connected to the input/output interface through a second node;

a first transistor including a first oxide semiconductor film as a semiconductor layer;

a second transistor including a second oxide semiconductor film as a semiconductor layer;

a first capacitor electrically connected to the first node through a source and a drain of the first transistor; and

a second capacitor electrically connected to the second node through a source and a drain of the second transistor,

wherein switching of the first and second transistors is controlled by the power control circuit,

wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal,

wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal,

wherein the first capacitor is electrically connected to the cache memory through the first node, and

wherein the second capacitor is electrically connected to the input/output interface through the second node.

7. The semiconductor device according to claim 6, further comprising:

a first switch between the power supply circuit and the first node; and

a second switch between the power supply circuit and the second node,

wherein switching of the first and second switches is controlled by the power control circuit.

8. The semiconductor device according to claim 7,

wherein the first transistor is stacked with the first switch, and

wherein the second transistor is stacked with the second switch.

9. The semiconductor device according to claim 6,

wherein the power control circuit turns off the first transistor before performing power gating on the cache memory,

wherein the power control circuit turns on the first transistor after stopping power gating of the cache memory,

wherein the power control circuit turns off the second transistor before performing power gating on the input/output interface, and

wherein the power control circuit turns on the second transistor after stopping power gating of the input/output interface.

10. A semiconductor device comprising:

a bus line;

a signal processing circuit;

a cache memory configured to be supplied with a first address signal from the signal processing circuit through the bus line;

an input/output interface configured to be supplied with a second address signal from the signal processing circuit through the bus line;

a sub-signal processing circuit configured to be booted up by the signal processing circuit;

an address monitoring circuit acquiring the first address signal and the second address signal;

a power control circuit performing power gating on the signal processing circuit, the cache memory, and the input/output interface;

a power supply circuit electrically connected to the signal processing circuit through a first node, electrically connected to the cache memory through a second node, and electrically connected to the input/output interface through a third node;

a first transistor including a first oxide semiconductor film as a semiconductor layer;

a second transistor including a second oxide semiconductor film as a semiconductor layer;

a third transistor including a third oxide semiconductor film as a semiconductor layer;

a first capacitor electrically connected to the first node through a source and a drain of the first transistor;

a second capacitor electrically connected to the second node through a source and a drain of the second transistor; and

a third capacitor electrically connected to the third node through a source and a drain of the third transistor,

wherein switching of the first to third transistors is controlled by the power control circuit,

wherein the power control circuit is configured to select whether power gating of the signal processing circuit is performed or not according to whether the sub-signal processing circuit is booted up or not,

wherein the power control circuit is configured to select whether power gating of the cache memory is performed or not in response to the first address signal,

wherein the power control circuit is configured to select whether power gating of the input/output interface is performed or not in response to the second address signal,

wherein the first capacitor is electrically connected to the signal processing circuit through the first node,

wherein the second capacitor is electrically connected to the cache memory through the second node, and

wherein the third capacitor is electrically connected to the input/output interface through the third node.

11. The semiconductor device according to claim 10, further comprising:

a first switch between the power supply circuit and the first node;

a second switch between the power supply circuit and the second node; and

a third switch between the power supply circuit and the third node,

wherein switching of the first to third switches is controlled by the power control circuit.

12. The semiconductor device according to claim 10,

wherein the power control circuit turns off the first transistor before performing power gating on the signal processing circuit,

wherein the power control circuit turns on the first transistor after stopping power gating of the signal processing circuit,

wherein the power control circuit turns off the second transistor before performing power gating on the cache memory,

wherein the power control circuit turns on the second transistor after stopping power gating of the cache memory,

wherein the power control circuit turns off the third transistor before performing power gating on the input/output interface, and

wherein the power control circuit turns on the third transistor after stopping power gating of the input/output interface.

13. The semiconductor device according to claim 10,

wherein the first to third transistors and the first to third switches are stacked.

14. The semiconductor device according to claim 10,

wherein the signal processing circuit comprises a volatile register and a nonvolatile register.

15. The semiconductor device according to claim 14,

wherein the nonvolatile register comprises a fourth transistor including an oxide semiconductor film as a semiconductor layer.

16. The semiconductor device according to claim 15,

wherein the volatile register comprises a fifth transistor including a portion of a single crystal silicon substrate as a semiconductor layer.

17. The semiconductor device according to claim 16,

wherein the first transistor is stacked with the second transistor.