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Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency

  • US 10,088,891 B2
  • Filed: 09/23/2014
  • Issued: 10/02/2018
  • Est. Priority Date: 09/23/2013
  • Status: Active Grant
First Claim
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1. A method for managing power in a processor having multiple cores, wherein each core of the multiple cores includes different partitioned power regions and each power region of the partitioned power regions is partitioned into multiple lanes with each lane of the multiple lanes including a sub-bank of an associated queue and processor components, comprising:

  • controlling power to the processor by independently turning on or off electrical power to all lanes in the processor respectively, wherein the all lanes include a sum of the multiple lanes of the partitioned power regions in the multiple cores, wherein the turning on or off the electrical power to all lanes includes turning on or off the electrical power to components within each lane of the all lanes;

    applying an optimization mechanism within a time slice to determine a combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance of the processor under a power constraint budget, wherein the optimization mechanism includes a configuration sampling phase, a surrogate surface fitting phase, an optimization phase, and a steady phase in the time slice and further comprises;

    running a workload for a sample period during the configuration sampling phase on the multiple cores of the processor to collect a set of sampled data for each individual core of the multiple cores;

    constructing a response surface model for each individual core, wherein the response surface model comprises an interpolating model of the partitioned power regions, and is fit to the set of sampled data for the corresponding individual core during the surrogate surface fitting phase;

    determining, based on an online optimization algorithm using an objective function based on the response surface models for the individual cores, the combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phase, wherein the response surface model for each individual core is different from the objective function.

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