Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency

• US 10,088,891 B2
• Filed: 09/23/2014
• Issued: 10/02/2018
• Est. Priority Date: 09/23/2013
• Status: Active Grant

• Current Assignee: Cornell University
• Original Assignee: Cornell University
• Inventors: Petrica, Paula, Izraelevitz, Adam M., Albonesi, David H., Shoemaker, Christine A.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Harrington, Cheri
• Application Number:
  US14/494,568
• Publication Number:
  US 20150185816A1
• Time in Patent Office: 1,470 Days
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.

Claims

1. A method for managing power in a processor having multiple cores, wherein each core of the multiple cores includes different partitioned power regions and each power region of the partitioned power regions is partitioned into multiple lanes with each lane of the multiple lanes including a sub-bank of an associated queue and processor components, comprising:

controlling power to the processor by independently turning on or off electrical power to all lanes in the processor respectively, wherein the all lanes include a sum of the multiple lanes of the partitioned power regions in the multiple cores, wherein the turning on or off the electrical power to all lanes includes turning on or off the electrical power to components within each lane of the all lanes;

applying an optimization mechanism within a time slice to determine a combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance of the processor under a power constraint budget, wherein the optimization mechanism includes a configuration sampling phase, a surrogate surface fitting phase, an optimization phase, and a steady phase in the time slice and further comprises;

running a workload for a sample period during the configuration sampling phase on the multiple cores of the processor to collect a set of sampled data for each individual core of the multiple cores;

constructing a response surface model for each individual core, wherein the response surface model comprises an interpolating model of the partitioned power regions, and is fit to the set of sampled data for the corresponding individual core during the surrogate surface fitting phase;

determining, based on an online optimization algorithm using an objective function based on the response surface models for the individual cores, the combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phase, wherein the response surface model for each individual core is different from the objective function.

2. The method of claim 1, wherein:

the partitioned power regions include three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region.

3. The method of claim 2, wherein:

the front end region includes a fetch, a decode, a reorder buffer, a rename, and a dispatch stage;

the execute region includes an issue queue, a register file, and a functional unit; and

the memory region includes a load queue and a store queue.

4. The method of claim 1, wherein:

a lane of the multiple lanes further includes a physical gating mechanism and a logical correctness mechanism.

5. The method of claim 4, wherein the physical gating mechanism includes a sleep transistor for power gating.

6. The method of claim 1, wherein the processor includes 32 cores.

7. The method of claim 1, wherein the time slice is greater than or equal to 100 ms.

8. The method of claim 1, wherein:

the response surface models are performance response surface models or power response surface models;

the processor operates under the combination of powered lanes within different cores during the steady phase; and

the configuration sampling phase, the surrogate surface fitting phase, and the optimization phase together are within a fraction of the time slice.

9. The method of claim 8, wherein:

the online optimization algorithm that optimizes performance under the power constraint budget for the workload is applied to a multivariate statistical experimental design with a set of responses and a set of factors;

a response of the set of responses is a sampled datum collected from the workload running for the sampling period; and

a factor of the set of factors is a power region of the partitioned power regions in a core of the multiple cores.

10. The method of claim 9, wherein the response of the set of responses is a sampled throughput datum or a sampled power consumption datum collected from the workload running for the sampling period.

11. The method of claim 9, wherein:

the partitioned power regions include three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region; and

the factor of the set of factors is the front end region, the execute region, or the memory region.

12. The method of claim 11, wherein the response of the set of responses is the sampled datum collected from the workload runs for the sampling period on a full factorial design of the factors, a Box-Behnken design of the factors, or a fractional factorial design of the factors.

13. The method of claim 12, wherein the response of the set of responses is the sampled datum collected from the workload running for a 1 ms sampling period.

14. The method of claim 12, wherein the response of the set of responses is an average of the set of sampled data collected for a plurality of subintervals of the sampling period.

15. The method of claim 8, wherein the performance response surface models or the power response surface models are constructed using a first order polynomial, a second order polynomial, or an interpolating model that places a Radial Basis Function (RBF) at each sampled datum.

16. The method of claim 8, wherein the online optimization algorithm incorporates a genetic algorithm.

17. A system having a computer processor having multiple cores, comprising:

a processor including multiple cores, each core of the multiple cores being a computer processor core and being partitioned into multiple power regions, wherein each power region of the multiple power regions is further partitioned into multiple lanes and each lane of the multiple lanes includes a sub-bank of an associated queue;

a first storage storing a power constraint budget for a workload to be performed by the system;

a second storage storing the workload; and

a controller coupled to the first and second storages and all lanes in the processor, wherein the all lanes include a sum of the multiple lanes of the multiple power regions in the multiple cores, the controller operable to adopt an optimization mechanism to determine, within a time slice, a combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance under the power constraint budget for the workload, wherein components within each lane of the all lanes are powered on or off together under a control of the controller, and wherein the optimization mechanism includes a configuration sampling phase, a surrogate surface fitting phase, an optimization phase, and a steady phase in the time slice and further comprises;

running a workload for a sample period during the configuration sampling phase on the multiple cores of the processor to collect a set of sampled data for each individual core of the multiple cores;

constructing a response surface model for each individual core, wherein the response surface model comprises an interpolating model of the multiple power regions, and is fit to the set of sampled data for the corresponding individual core during the surrogate surface fitting phase;

determining, based on an online optimization algorithm using an objective function based on the response surface models for the individual cores, the combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phase, wherein the response surface model for each individual core is different from the objective function.

18. The system of claim 17, wherein:

the partitioned power regions include three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region.

19. The system of claim 18, wherein:

the front end region includes a fetch, a decode, a reorder buffer, a rename, and a dispatch stage;

the execute region includes an issue queue, a register file, and a functional unit; and

the memory region includes a load queue and a store queue.

20. The system of claim 17, wherein:

a lane of the multiple lanes further includes a physical gating mechanism and a logical correctness mechanism.

21. The system of claim 20, wherein the physical gating mechanism includes a sleep transistor for power gating.

22. The system of claim 17, wherein the processor includes 32 cores.

23. The system of claim 17, wherein the time slice is greater than or equal to 100 ms.

24. The system of claim 17, wherein:

the response surface models are performance response surface models or power response surface models;

the processor operates under the combination of powered lanes within different cores during the steady phase; and

the configuration sampling phase, the surrogate surface fitting phase, and the optimization phase together are within a fraction of the time slice.

25. The system of claim 24, wherein:

the online optimization algorithm that optimizes performance under the power constraint budget for the workload is applied to a multivariate statistical experimental design with a set of responses and a set of factors;

a response of the set of responses is a sampled datum collected from the workload running for the sampling period; and

a factor of the set of factors is a power region of the multiple power regions in a core of the multiple cores.

26. The system of claim 25, wherein the response of the set of responses is a sampled throughput datum or a sampled power consumption datum collected from the workload running for the sampling period.

27. The system of claim 25, wherein:

the partitioned power regions include three power regions each comprising a plurality of pipeline stages;

a front end region, an execute region, and a memory region; and

the factor of the set of factors is the front end region, the execute region, or the memory region.

28. The system of claim 27, wherein the response of the set of responses is the sampled datum collected from the workload running for the sampling period on a full factorial design of the factors, a Box-Behnken design of the factors, or a fractional factorial design of the factors.

29. The system of claim 28, wherein the response of the set of responses is the sampled datum collected from the workload running for a 1 ms sampling period.

30. The system of claim 28, wherein the response of the set of responses is an average of the set of sampled data collected for a plurality of subintervals of the sampling period.

31. The system of claim 24, wherein the performance response surface models or the power response surface models are constructed using a first order polynomial, a second order polynomial, or an interpolating model that places a Radial Basis Function (RBF) at each sampled datum.

32. The system of claim 24, wherein the online optimization algorithm incorporates a genetic algorithm.

33. A method for managing power in a processor having multiple cores, wherein each core of the multiple cores includes different partitioned power regions and each power region of the partitioned power regions is partitioned into multiple lanes with each lane of the multiple lanes including a sub-bank of an associated queue and processor components, comprising:

controlling power to the processor by independently controlling electrical power to all lanes in the processor respectively, wherein the all lanes include sum of the multiple lanes of the partitioned power regions in the multiple cores;

controlling power levels supplied to components within each lane of the all lanes by a gating control; and

applying an optimization mechanism within a time slice to determine a combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance of the processor under a power constraint budget, wherein the optimization mechanism includes a configuration sampling phase, a surrogate surface fitting phase, an optimization phase, and a steady phase in the time slice and further comprises;

running a workload for a sample period during the configuration sampling phase on the multiple cores of the processor to collect a set of sampled data for each individual core of the multiple cores;

constructing a response surface model for each individual core, wherein the response surface model comprises an interpolating model of the partitioned power regions, and is fit to the set of sampled data for the corresponding individual core during the surrogate surface fitting phase;

determining, based on an online optimization algorithm using an objective function based on the response surface models for the individual cores to solve a constrained integer global optimization problem, the combination of powered-on lanes of the all lanes within different cores of the multiple cores of the processor that optimizes performance under the power constraint budget for the workload during the optimization phase, wherein the response surface model for each individual core is different from the objective function.

34. The method of claim 33, wherein the gating control in controlling electrical power to a lane is by clock gating, power gating, or voltage scaling.