Random number generator
First Claim
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1. An integrated random signal generation circuit comprising:
- a plurality of delay element assemblies, each delay element assembly having an adjustable delay;
a first logic gate having a first input, a second input, and an output;
a second logic gate having a first input, a second input, and an output, the output of the first logic gate coupled through at least one first delay element assembly of the plurality of delay element assemblies to the first input of the second logic gate, the output of the second logic gate coupled through at least one second delay element assembly of the plurality of delay element assemblies to the first input of the first logic gate, wherein each delay element assembly includes;
a first sub-assembly configured to provide a non-adjustable delay; and
a second sub-assembly configured to provide an adjustable delay.
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Abstract
An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.
10 Citations
14 Claims
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1. An integrated random signal generation circuit comprising:
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a plurality of delay element assemblies, each delay element assembly having an adjustable delay; a first logic gate having a first input, a second input, and an output; a second logic gate having a first input, a second input, and an output, the output of the first logic gate coupled through at least one first delay element assembly of the plurality of delay element assemblies to the first input of the second logic gate, the output of the second logic gate coupled through at least one second delay element assembly of the plurality of delay element assemblies to the first input of the first logic gate, wherein each delay element assembly includes; a first sub-assembly configured to provide a non-adjustable delay; and a second sub-assembly configured to provide an adjustable delay. - View Dependent Claims (2, 3, 4, 5)
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6. A random number generation circuit, comprising:
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a first logic gate; a second logic gate; a first adjustable delay element assembly coupled in series between an output of the first logic gate and an input of the second logic gate; a second adjustable delay element assembly coupled in series between an output of the second logic gate and an input of the first logic gate; and a digitizing circuit coupled to an output of the second adjustable delay element, wherein the first and second adjustable delay element assemblies each include a first sub-assembly configured to provide a fixed delay and a second sub-assembly configured to provide a selectable delay. - View Dependent Claims (7, 8, 9, 10)
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11. A method of generating a random number, comprising:
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passing a first signal from a first logic gate into a first adjustable delay element assembly, the first adjustable delay element having a first sub-assembly circuit configured to provide a first non-adjustable delay and a second sub-assembly configured to provide a first adjustable delay; passing a second signal from the first adjustable delay element assembly into a second logic gate; passing a third signal from the second logic gate into a second adjustable delay element assembly, the second adjustable delay element assembly having a third sub-assembly configured to provide a second fixed delay and a fourth sub-assembly configured to provide a second selectable delay; passing a fourth signal from the second adjustable delay element assembly into the first logic gate; passing the fourth signal into a digitizing circuit; and producing the random number with the digitizing circuit. - View Dependent Claims (12, 13, 14)
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Specification