Filtering of redundently scheduled write passes

• US 10,089,231 B1
• Filed: 11/07/2017
• Issued: 10/02/2018
• Est. Priority Date: 07/14/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Friedmann, Simon H., Kurup, Girish G., Kaltenbach, Markus, Mayer, Ulrich, Recktenwald, Martin
• Primary Examiner(s): Ruiz, Angelica
• Application Number:
  US15/805,549
• Time in Patent Office: 329 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0857 by multiple requestors
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/655 Same page detection

Abstract

Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.

Claims

1. A method of improving access to a cache by a processing unit, the method comprising:

storing one or more previous requests to access data from a cache;

retrieving a current request to access data from the cache in a read pass that will execute in a stream of instructions, the stream of instructions including one or more read passes, followed by one or more write passes;

determining whether the current request is seeking the same data from the cache as at least one of the one or more previous requests in a lower level cache, the current request seeking the same data as at least one of the one or more previous requests if each is seeking a same logical address of a translation look aside buffer containing a list of resource entries available in the cache, and, if the current request does not seek the same data as at least one of the one or more previous requests, terminating execution;

determining whether the at least one of the one or more previous requests seeking the same data from the cache was successful in arbitrating access to a processing unit when seeking access, at least one of the one or more previous requests successful in arbitrating access to the processing unit if the processing unit is not blocked by another thread, a load/store unit is not accessing the processing unit simultaneously, or another concurrent read/write blocked access to the processing unit, and, if none of the previous requests seeking the same data from the cache was successful, terminating execution;

determining whether at least one previous cache write access followed the previous requests seeking the same data; and

suppressing a next cache write access in a write pass in the stream of instructions if the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to the processing unit, the next cache write access preventing concurrent read accesses if not suppressed.