Memory devices for pattern matching
First Claim
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1. A memory device, comprising:
- an array of memory cells;
a controller;
a plurality of key registers to store a representation of a key word to be searched; and
a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells;
wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;
wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;
wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and
wherein the memory device is further configured to determine an error count by;
precharging a selected data line of a string of memory cells of the array of memory cells;
sensing on the selected data line;
if the selected data line does not discharge, storing an error count value of zero;
if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;
if the data line does not discharge, storing an error count value equal to the reference current level; and
if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and
storing an error count based on the reference current at which the data line remains charged.
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Abstract
Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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Citations
16 Claims
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1. A memory device, comprising:
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an array of memory cells; a controller; a plurality of key registers to store a representation of a key word to be searched; and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells; wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries; wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells; wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and wherein the memory device is further configured to determine an error count by; precharging a selected data line of a string of memory cells of the array of memory cells; sensing on the selected data line; if the selected data line does not discharge, storing an error count value of zero; if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges; if the data line does not discharge, storing an error count value equal to the reference current level; and if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and storing an error count based on the reference current at which the data line remains charged. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory device, comprising:
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an array of memory cells; a controller; a plurality of key registers to store a representation of a key word to be searched; and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a key register of the plurality of key registers to compare to data stored in the array of memory cells; wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries; wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells; wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and wherein each multiplexer of the plurality of multiplexers is configured to; receive a plurality of voltage levels; apply a first voltage level of the plurality of voltage levels to one access line of a corresponding string of memory cells of the array of memory cells when the bit of the key word has a first value; apply a second voltage level of the plurality of voltage levels to the one access line of the corresponding string of memory cells when the bit of the key word has a second value different than the first value; apply the second voltage level to an other access line of the corresponding string of memory cells when the bit of the key word has the first value; apply the first voltage level to the other access line of the corresponding string of memory cells when the bit of the key word has the second value; and apply a particular voltage level of the plurality of voltage levels to remaining access lines of the corresponding string of memory cells regardless of the value of the bit of the key word; and wherein the memory device is further configured to determine an error count by; precharging a selected data line of a string of memory cells of the array of memory cells; sensing on the selected data line; if the selected data line does not discharge, storing an error count value of zero; if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges; if the data line does not discharge, storing an error count value equal to the reference current level; and if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and storing an error count based on the reference current at which the data line remains charged. - View Dependent Claims (8, 9, 10, 11)
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12. A memory device, comprising:
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an array of memory cells; a controller; a plurality of key registers to store a representation of a key word to be searched; and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a corresponding key register of the plurality of key registers to compare to data stored in the array of memory cells; wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries; wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells; wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; wherein each multiplexer of the plurality of multiplexers is configured to apply respective voltage levels to a plurality of access lines of a corresponding string of memory cells of the array of memory cells in response to its selected representation of a bit of the key word; and wherein the memory device is further configured to determine an error count by; precharging a selected data line of a string of memory cells of the array of memory cells; sensing on the selected data line; if the selected data line does not discharge, storing an error count value of zero; if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges; if the data line does not discharge, storing an error count value equal to the reference current level; and if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and storing an error count based on the reference current at which the data line remains charged. - View Dependent Claims (13, 14, 15, 16)
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Specification