Memory device including current generator plate

• US 10,090,024 B2
• Filed: 12/15/2017
• Issued: 10/02/2018
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/844,007
• Publication Number:
  US 20180108385A1
• Time in Patent Office: 291 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second conductive materials; memory cells located along the pillars; first select gates located in a third level of the apparatus between the first and second levels, with each of the first select gates being located along a segment of a respective pillar among the pillars; second select gates located in a fourth level of the apparatus between the first and third levels; and a conductive plate located in a fifth level of the apparatus between the first and fourth levels, with each of the pillars extending through the conductive plate.

Claims

1. An apparatus comprising:

a first data line and a second data line;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the first data line and a first memory cell string, wherein the first select gate is directly coupled to the second select gate, and the second select gate is directly coupled to the first transistor;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the first data line and a second memory cell string, wherein the third select gate is directly coupled to the fourth select gate, and the fourth select gate is directly coupled to the second transistor;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the second data line and a third memory cell string, wherein the fifth select gate is directly coupled to the sixth select gate, and the sixth select gate is directly coupled to the third transistor; and

a conductive line coupled to a gate of each of the first, second, and third transistors.

2. The apparatus of claim 1, further comprising a control line, wherein the first, second, and third memory cell strings share the control line.

3. The apparatus of claim 1, wherein the conductive line includes a conductive plate of polycrystalline silicon, and the gate of each of the first, second, and third transistors is part of the conductive plate of polycrystalline silicon.

4. The apparatus of claim 1, wherein the conductive line is to receive a voltage during an erase operation of the apparatus in order to generate gate-induced drain leakage current at the transistors during the erase operation.

5. The apparatus of claim 1, wherein the first, second, and third memory strings are included in a same block of memory cells.

6. The apparatus of claim 1, wherein the first, second, and third memory strings are included in different block of memory cells.

7. The apparatus of claim 4, wherein the conductive plate and the select line have different materials.

8. An apparatus comprising:

a first data line and a second data line;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the first data line and a first memory cell string;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the first data line and a second memory cell string;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the second data line and a third memory cell string;

a conductive line coupled to agate of each of the first, second, and third transistors; and

a control line, wherein among the first, second, and third memory cell strings, only the first and second memory cell strings share the control line.

9. An apparatus comprising:

a first data line and a second data line;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the first data line and a first memory cell string;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the first data line and a second memory cell string;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the second data line and a third memory cell string;

a conductive line coupled to a gate of each of the first, second, and third transistors;

a source;

a first additional select gate, and a second additional select gate coupled in series with the first additional select gate between the source the first memory cell string;

a third additional select gate, and a fourth additional select gate coupled in series with the third additional select gate between the source and the second memory cell string; and

a fifth additional select gate, and a sixth additional select gate coupled in series with the fifth additional select gate between the source and the third memory cell string.

10. An apparatus comprising:

a first data line and a second data line;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the first data line and a first memory cell string;

a third select gate, a fourth select gate, and a second transistor coupled in series wilt the third and fourth select gates between the first data line and a second memory cell string;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the second data line and a third memory cell string;

a conductive line coupled to a gate of each of the first, second, and third transistors; and

a select line coupled to the first and fifth select gates, wherein the conductive line includes a conductive plate, and the conductive lines plate has a thickness greater than a thickness of the select line.

11. An apparatus comprising:

a source;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the source and a first memory cell string, wherein the first select gate is directly coupled to the second select gate, and the second select gate is directly coupled to the first transistor;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the source and a second memory cell string, wherein the third select gate is directly coupled to the fourth select gate, and the fourth select gate is directly coupled to the second transistor;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the source and a third memory cell string, wherein the fifth select gate is directly coupled to the sixth select gate, and the sixth select gate is directly coupled to the third transistor; and

a conductive line coupled to a gate of each of the first, second, and third transistors.

12. The apparatus of claim 11, further comprising a control line, wherein the first, second, and third memory cell strings share the control line.

13. The apparatus of claim 11, wherein the conductive line includes a conductive plate of polycrystalline silicon, and the gate of each of the first, second, and third transistors is part of the conductive plate of polycrystalline silicon.

14. The apparatus of claim 11, wherein the conductive line is to receive a voltage during an erase operation of the apparatus in order to generate gate-induced drain leakage current at the transistors during the erase operation.

15. An apparatus comprising:

a source;

a first select gate, a second select gate, and a first transistor coupled in series with the first and second select gates between the source and a first memory cell string;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the source and a second memory cell string;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the source and a third memory cell string;

a conductive line coupled to a gate of each of the first, second, and third transistors; and

a control line, wherein among the first, second, and third memory cell strings, only the first and second memory cell strings share the control line.

16. An apparatus comprising:

a source;

a first select gate a second select gate, and a first transistor coupled in series with the first and second select gates between the source and a first memory cell string;

a third select gate, a fourth select gate, and a second transistor coupled in series with the third and fourth select gates between the source and a second memory cell string;

a fifth select gate, a sixth select gate, and a third transistor coupled in series with the fifth and sixth select gates between the source and a third memory cell string;

a conductive line coupled to a gate of each of the first, second, and third transistors;

a first data line and a second data line;

a first additional select gate, a second select gate, and a first additional transistor coupled in series with the first and second additional select gates between the first data line and the first memory cell string;

a third additional select gate, a fourth additional select gate, and a second additional transistor coupled in series with the third and fourth additional select gates between the first data line and a second memory cell string; and

a fifth additional select gate, a sixth additional select gate, and a third additional transistor coupled in series with the fifth and sixth additional select gates between the second data line and a third memory cell string.

17. A method comprising:

applying a first voltage to a first line coupled to a transistor of a memory device during an operation of retrieving information from a memory cell of a memory cell string of the memory device;

applying a second voltage to a second line coupled to a select gate of the memory device during the operation, the transistor and the select gate being coupled in series between the memory cell string and a conductive line of the memory device;

applying a third voltage to the first line during an erase operation of the memory device, the third voltage having a value greater than a value of a supply voltage of the memory device; and

placing the second line in a float state during the erase operation.

18. The method of claim 17, further comprising:

applying a fourth voltage to the conductive line during the erase operation, the fourth voltage having a value greater than the value of the third voltage.

19. The method of claim 17, further comprising:

placing the conductive line in a float state during the erase operation.

20. The method of claim 17, further comprising:

placing a third line coupled to an additional select gate in a float state during the erase operation, the additional select gate being coupled in series with the select gate and the transistor between the memory cell string and the conductive line.