Nonvolatile semiconductor memory device
First Claim
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1. A method for controlling a memory device,the memory device including:
- a first memory unit includinga first selection transistor,a first memory cell,a second memory cell, anda second selection transistor;
a second memory unit includinga third selection transistor,a third memory cell,a fourth memory cell, anda fourth selection transistor;
a bit line connected to the first selection transistor of the first memory unit and the third selection transistor of the second memory unit;
a source line connected to the second selection transistor of the first memory unit and the fourth selection transistor of the second memory unit;
a first word line connected to a gate of the first memory cell and a gate of the third memory cell;
a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell;
a first select gate line connected to a gate of the first selection transistor; and
a second select gate line connected to a gate of the third selection transistor, the method including;
performing a first erasing operation of erasing data stored in the first memory cell and data stored in the second memory cell without erasing data stored in the third memory cell and data stored in the fourth memory cell.
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Abstract
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
49 Citations
16 Claims
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1. A method for controlling a memory device,
the memory device including: -
a first memory unit including a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor; a second memory unit including a third selection transistor, a third memory cell, a fourth memory cell, and a fourth selection transistor; a bit line connected to the first selection transistor of the first memory unit and the third selection transistor of the second memory unit; a source line connected to the second selection transistor of the first memory unit and the fourth selection transistor of the second memory unit; a first word line connected to a gate of the first memory cell and a gate of the third memory cell; a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; a first select gate line connected to a gate of the first selection transistor; and a second select gate line connected to a gate of the third selection transistor, the method including; performing a first erasing operation of erasing data stored in the first memory cell and data stored in the second memory cell without erasing data stored in the third memory cell and data stored in the fourth memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device, comprising:
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a first memory unit including a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor; a second memory unit including a third selection transistor, a third memory cell, a fourth memory cell, and a fourth selection transistor; a bit line connected to the first selection transistor of the first memory unit and the third selection transistor of the second memory unit; a source line connected to the second selection transistor of the first memory unit and the fourth selection transistor of the second memory unit; a first word line connected to a gate of the first memory cell and a gate of the third memory cell; a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; a first select gate line connected to a gate of the first selection transistor; a second select gate line connected to a gate of the third selection transistor; and a control circuit configured to perform a first erasing operation of selectively erasing data stored in the first memory cell and data stored in the second memory cell. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification
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Current AssigneeKioxia Corporation
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Original AssigneeToshiba Memory Corporation (Kioxia Corporation)
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InventorsMaeda, Takashi
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Primary Examiner(s)Nguyen, Tuan T
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Application NumberUS15/915,701Publication NumberTime in Patent Office208 DaysField of SearchUS Class CurrentCPC Class CodesG11C 16/0483 comprising cells having sev...G11C 16/08 Address circuits; Decoders;...G11C 16/10 Programming or data input c...G11C 16/14 Circuits for erasing electr...G11C 16/16 for erasing blocks, e.g. ar...G11C 16/26 Sensing or reading circuits...G11C 16/30 Power supply circuitsG11C 5/145 Applications of charge pump...H10B 43/27 the channels comprising ver...H10B 43/35 with cell select transistor...
