Semiconductor device and manufacturing method thereof

• US 10,090,157 B2
• Filed: 05/19/2017
• Issued: 10/02/2018
• Est. Priority Date: 06/10/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fung, Ka-Hing
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US15/599,656
• Publication Number:
  US 20170358646A1
• Time in Patent Office: 501 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire. When viewed in cross section taken along third direction, each nanowire in nanowire structure is differently shaped from other nanowires, and each nanowire has substantially same cross-sectional area as other nanowires in nanowire structure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a second direction over a substrate;

patterning the stacked structure into a fin structure extending along a first direction substantially perpendicular to the second direction;

removing a portion of the first semiconductor layers between adjacent second semiconductor layers to form a nanowire structure;

forming a gate structure extending in a third direction over a first portion of the nanowire structure so that the gate structure wraps around the second semiconductor layers, the third direction being substantially perpendicular to both the first direction and the second direction;

forming source/drain regions over a second portion of the nanowire structure located on opposing sides of the nanowire structure so that the source/drain regions wrap around the second semiconductor layers,

wherein a thickness of a second semiconductor layer furthest from the substrate extending in the second direction is greater than other second semiconductor layers in the nanowire structure, and a thickness of a second semiconductor layer closest to the substrate extending in the second direction is smaller than other second semiconductor layers in the nanowire structure.

2. The method according to claim 1, wherein a width in the third direction of a second semiconductor layer furthest from the substrate is less than other second semiconductor layers in the nanowire structure, and a width in the third direction of a second semiconductor layer closest to the substrate is greater than other second semiconductor layers in the nanowire structure.

3. The method according to claim 1, wherein the patterning the stacked structure into a fin structure comprises:

isotropically etching a second semiconductor layer furthest from the substrate; and

anisotropically etching another second semiconductor layer closer to the substrate.

4. The method according to claim 1, further comprising:

forming an isolation insulating layer over the fin structure;

forming a cover layer over the isolation insulating layer;

patterning the cover layer so as to form an opening and remaining boundary portions; and

recessing the isolation insulating layer through the opening to expose a central region of the fin structure, so that end regions of the fin structure remain buried in the isolation insulating layer, and

wherein the portion of the first semiconductor layers removed between adjacent first semiconductor layers is in the central region.

5. The method according to claim 1, wherein the forming the gate structure comprises:

forming a conformal gate dielectric layer wrapping around the second semiconductor layers; and

forming a gate electrode layer on the gate dielectric layer wrapping around the second semiconductor layers.

6. The method according to claim 1, wherein the portion of the first semiconductor layers removed between adjacent second semiconductor layers is removed by isotropically etching the first semiconductor layers between adjacent second semiconductor layers.

7. The method according to claim 1, wherein the first semiconductor layers are formed to a substantially same thickness in the second direction.

13. The method according to claim 1, wherein the first portion of the first semiconductor layers removed between adjacent second semiconductor layers is removed by isotropically etching the first semiconductor layers between adjacent second semiconductor layers.

14. The method according to claim 1, wherein the first semiconductor layers are formed to a substantially same thickness in the second direction.

8. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a second direction over a substrate;

patterning the stacked structure into a fin structure extending along a first direction substantially perpendicular to the second direction;

removing a first portion of the first semiconductor layers between adjacent second semiconductor layers so that a second portion of the first semiconductor layers remains between adjacent second semiconductor layers to form a nanowire structure;

forming a gate structure extending in a third direction over a first portion of the nanowire structure so that the gate structure wraps around the second semiconductor layers, the third direction being substantially perpendicular to both the first direction and the second direction,

wherein a width of a second portion of the first semiconductor layer furthest from the substrate extending in the third direction is less than other second portions of the first semiconductor layers in the nanowire structure, and a width of a second portion of the first semiconductor layer closest to the substrate extending in the third is greater than other second portions of the first semiconductor layer in the nanowire structure.

9. The method according to claim 8, wherein the forming the gate structure comprises:

forming a conformal gate dielectric layer wrapping around the second semiconductor layers; and

forming a gate electrode layer on the gate dielectric layer wrapping around the second semiconductor layers.

10. The method according to claim 8, wherein a width in the third direction of second portion of any first semiconductor layer is less than a width in the third direction of any immediately adjacent second semiconductor layer.

11. The method according to claim 8, wherein the patterning the stacked structure into a tin structure comprises:

isotropically etching a second semiconductor layer furthest from the substrate; and

anisotropically etching another second semiconductor layer closer to the substrate.

12. The method according to claim 8, further comprising:

forming an isolation insulating layer over the fin structure;

forming a cover layer over the isolation insulating layer;

patterning the cover layer so as to form an opening and remaining boundary portions; and

recessing the isolation insulating layer through the opening to expose a central region of the fin structure, so that end regions of the fin structure remain buried in the isolation insulating layer, and

wherein the portion of the first semiconductor layers removed between adjacent first semiconductor layers is in the central region.

15. A method of manufacturing a semiconductor device, comprising:

forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a second direction over a substrate;

patterning the stacked structure into a fin structure extending along a first direction substantially perpendicular to the second direction, wherein the patterning includes;

isotropic etching of an uppermost second semiconductor layer, anisotropic etching of lower second semiconductor layers, and isotropic etching of the first semiconductor layers to form a nanowire structure; and

forming a gate structure extending in a third direction over a first portion of the nanowire structure so that the gate structure wraps around the second semiconductor layers, the third direction being substantially perpendicular to both the first direction and the second direction,

wherein the second semiconductor layer located furthest from the substrate is substantially trapezoidal-shaped when viewed in a cross section, and

the second semiconductor layer located closest to the substrate is substantially rectangular-shaped when viewed in the cross section.

16. The method according to claim 15, further comprising forming source/drain regions over a second portion of the nanowire structure, the second portion of the nanowire structure being located on opposing sides of the gate structure.

17. The method according to claim 16, wherein the gate structure is a sacrificial gate structure, and further comprising after forming the source/drain regions:

removing the sacrificial gate structure to form a gate space; and

forming a high-k gate dielectric layer and a metal gate electrode layer in the gate space.

18. The method according to claim 17, wherein the high-k gate dielectric layer and the metal gate electrode layer wraps around the second semiconductor layers.

19. The method according to claim 15, further comprising:

forming an isolation insulating layer over the fin structure;

forming a cover layer over the isolation insulating layer;

patterning the cover layer so as to form an opening and remaining boundary portions; and

recessing the isolation insulating layer through the opening to expose a central region of the fin structure, so that end regions of the fin structure remain buried in the isolation insulating layer, and

wherein the portion of the first semiconductor layers removed between adjacent first semiconductor layers is in the central region.

20. The method according to claim 15, wherein the first semiconductor layers are formed to a substantially same thickness in the second direction.