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Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

  • US 10,090,286 B2
  • Filed: 10/20/2017
  • Issued: 10/02/2018
  • Est. Priority Date: 08/13/2015
  • Status: Active Grant
First Claim
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1. A method to construct a package structure, comprising:

  • fabricating a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a bulk substrate layer, a buried oxide layer disposed on the bulk substrate layer, an active silicon layer disposed on the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer, wherein the active silicon layer comprises active circuitry and an integrated optical waveguide structure;

    bonding a first surface of an interposer substrate to the BEOL structure of the first integrated circuit chip;

    forming conductive through vias in the interposer substrate in alignment with contact pads of the BEOL structure, and forming contact pads on a second surface of the interposer substrate;

    removing the bulk substrate layer to expose the buried oxide layer;

    forming one or more inverted pad structures through the exposed buried oxide layer down to buried pads within the BEOL structure;

    forming solder bumps on the contact pads of the interposer substrate; and

    mounting an optoelectronics device to the first integrated circuit chip by bonding the optoelectronics device to ends of the inverted pad structures exposed through the buried oxide layer, and such that the optoelectronics device is aligned with a first end of the integrated optical waveguide structure of the first integrated circuit chip;

    mounting the photonics package to a first side of a package interposer;

    mounting a second integrated circuit chip to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and

    mounting an application board to the package interposer, wherein the application board has an integrated recess formed in one side of the application board, wherein at least a portion of the photonics package is disposed within the integrated recess of the application board; and

    further wherein the application board comprises a plurality of thermal vias formed therein in alignment with the integrated recess, wherein the photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias.

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