Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
First Claim
1. A method to construct a package structure, comprising:
- fabricating a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a bulk substrate layer, a buried oxide layer disposed on the bulk substrate layer, an active silicon layer disposed on the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer, wherein the active silicon layer comprises active circuitry and an integrated optical waveguide structure;
bonding a first surface of an interposer substrate to the BEOL structure of the first integrated circuit chip;
forming conductive through vias in the interposer substrate in alignment with contact pads of the BEOL structure, and forming contact pads on a second surface of the interposer substrate;
removing the bulk substrate layer to expose the buried oxide layer;
forming one or more inverted pad structures through the exposed buried oxide layer down to buried pads within the BEOL structure;
forming solder bumps on the contact pads of the interposer substrate; and
mounting an optoelectronics device to the first integrated circuit chip by bonding the optoelectronics device to ends of the inverted pad structures exposed through the buried oxide layer, and such that the optoelectronics device is aligned with a first end of the integrated optical waveguide structure of the first integrated circuit chip;
mounting the photonics package to a first side of a package interposer;
mounting a second integrated circuit chip to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and
mounting an application board to the package interposer, wherein the application board has an integrated recess formed in one side of the application board, wherein at least a portion of the photonics package is disposed within the integrated recess of the application board; and
further wherein the application board comprises a plurality of thermal vias formed therein in alignment with the integrated recess, wherein the photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias.
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Accused Products
Abstract
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
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Citations
20 Claims
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1. A method to construct a package structure, comprising:
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fabricating a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a bulk substrate layer, a buried oxide layer disposed on the bulk substrate layer, an active silicon layer disposed on the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer, wherein the active silicon layer comprises active circuitry and an integrated optical waveguide structure; bonding a first surface of an interposer substrate to the BEOL structure of the first integrated circuit chip; forming conductive through vias in the interposer substrate in alignment with contact pads of the BEOL structure, and forming contact pads on a second surface of the interposer substrate; removing the bulk substrate layer to expose the buried oxide layer; forming one or more inverted pad structures through the exposed buried oxide layer down to buried pads within the BEOL structure; forming solder bumps on the contact pads of the interposer substrate; and mounting an optoelectronics device to the first integrated circuit chip by bonding the optoelectronics device to ends of the inverted pad structures exposed through the buried oxide layer, and such that the optoelectronics device is aligned with a first end of the integrated optical waveguide structure of the first integrated circuit chip; mounting the photonics package to a first side of a package interposer; mounting a second integrated circuit chip to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and mounting an application board to the package interposer, wherein the application board has an integrated recess formed in one side of the application board, wherein at least a portion of the photonics package is disposed within the integrated recess of the application board; and
further wherein the application board comprises a plurality of thermal vias formed therein in alignment with the integrated recess, wherein the photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method to construct a package structure, comprising:
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fabricating a photonics package comprising; a first integrated circuit chip comprising an insulating layer, an active silicon layer disposed adjacent to the insulating layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer, wherein the active silicon layer comprises active circuitry and an integrated optical waveguide structure patterned from the active silicon layer; an optoelectronics device mounted on the insulating layer of the first integrated circuit chip in alignment with a portion of the integrated optical waveguide structure, and electrically connected to the active circuitry; and an interposer bonded to the BEOL structure of the first integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and wiring to provide electrical connections to the BEOL structure; and coupling the photonics package to a second integrated circuit chip by flip-chip bonding the interposer of the photonics package to an active surface of the second integrated circuit chip, wherein the second integrated circuit chip comprises a processor coupled to the active circuitry of the first integrated circuit chip; mounting the second integrated circuit to a first side of a package interposer comprising the first side and a second side opposite the first side with the photonics package disposed within a hole formed through the package interposer from the first side of the package interposer to the second side of the package interposer; and mounting an application board to the second side of the package interposer. - View Dependent Claims (17, 18, 19, 20)
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Specification