Display device and manufacturing method thereof

• US 10,090,373 B2
• Filed: 12/07/2017
• Issued: 10/02/2018
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Osame, Mitsuaki
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/834,564
• Publication Number:
  US 20180108725A1
• Time in Patent Office: 299 Days
• Field of Search: 257 66, 257 72, 257751, 257784
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 5/0017 with operator interface units
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.

Claims

1. A display device comprising:

a substrate;

a semiconductor layer over the substrate;

a gate electrode;

a gate insulating layer interposed between the gate electrode and the semiconductor layer;

a first insulating layer over the semiconductor layer;

a second insulating layer comprising organic material over the first insulating layer;

a wiring over the second insulating layer;

a third insulating layer over the wiring; and

a pixel electrode over the third insulating layer,

wherein the gate electrode comprises a first layer comprising titanium and a second layer comprising copper,

wherein the second layer is over the first layer,

wherein the second layer is narrower than the first layer, and

wherein the wiring comprises copper.

2. The display device according to claim 1, wherein the first insulating layer comprises a silicon oxynitride layer.

3. The display device according to claim 1, wherein the organic material is any one of polyimide, acrylic, polyamide, and polyimideamide.

4. The display device according to claim 1, wherein the third insulating layer comprises a silicon nitride layer or a silicon oxynitride layer.

5. The display device according to claim 1, wherein the first layer comprises a conductive layer comprising titanium and a conductive barrier layer comprising titanium nitride.

6. The display device according to claim 1, wherein the gate electrode is over the gate insulating layer.

7. A display device comprising:

a substrate;

a semiconductor layer over the substrate;

a gate electrode;

a gate insulating layer interposed between the gate electrode and the semiconductor layer;

a first insulating layer over the semiconductor layer;

a second insulating layer comprising organic material over the first insulating layer;

a wiring over the second insulating layer;

a third insulating layer over the wiring; and

a pixel electrode over the third insulating layer,

wherein the gate electrode comprises a first layer comprising titanium and a second layer comprising copper,

wherein the second layer is over the first layer,

wherein the second layer is narrower than the first layer,

wherein the wiring comprises copper, and

wherein the second insulating layer comprises a rounded portion in a vertical cross-sectional view of the second insulating layer.

8. The display device according to claim 7, wherein the first insulating layer comprises a silicon oxynitride layer.

9. The display device according to claim 7, wherein the organic material is any one of polyimide, acrylic, polyamide, and polyimideamide.

10. The display device according to claim 7, wherein the third insulating layer comprises a silicon nitride layer or a silicon oxynitride layer.

11. The display device according to claim 7, wherein the first layer comprises a conductive layer comprising titanium and a conductive barrier layer comprising titanium nitride.

12. The display device according to claim 7, wherein the gate electrode is over the gate insulating layer.