III-nitride light emitting device including porous semiconductor

• US 10,090,435 B2
• Filed: 06/01/2016
• Issued: 10/02/2018
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J., Epler, John E.
• Primary Examiner(s): Sayadian, Hrayr A
• Application Number:
  US15/170,161
• Publication Number:
  US 20160284935A1
• Time in Patent Office: 853 Days
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.

Claims

1. A method comprising:

growing a first III-nitride layer directly on a substrate;

making at least a portion of the first III-nitride layer porous;

growing a second III-nitride layer directly on the porous portion, the second layer comprising InGaN; and

growing a device structure directly on the second III-nitride layer, the device structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region.

2. The method of claim 1 further comprising:

forming a mask over the first III-nitride layer; and

forming a plurality of openings in the mask;

wherein growing a second III-nitride layer comprises growing by epitaxial lateral overgrowth.

3. The method of claim 2 wherein making at least a portion of the first III-nitride layer porous comprises making regions of the first III-nitride layer aligned with the plurality of openings porous.

4. The method of claim 1 wherein the second III-nitride layer has an in-plane lattice constant of at least 3.189 Å

.

5. The method of claim 1 further comprising:

forming n- and p-contacts electrically connected to the n- and p-type region, wherein the n- and p-contacts are both formed on a same side of the device structure;

connecting the device structure to a mount; and

removing the substrate.

6. The method of claim 1 wherein making at least a portion of the first III-nitride layer porous comprises making an entire thickness of the first III-nitride layer porous.

7. The method of claim 6 further comprising making at least a portion of the substrate porous.

8. The method of claim 1 wherein making at least a portion of the first III-nitride layer porous comprises making an entire thickness of the first III-nitride layer porous, such that porous material is in direct contact with the substrate.

9. The method of claim 1 wherein the second III-nitride layer has a composition of indium equal to or less than a composition of indium in the III-nitride light emitting layer.

10. The method of claim 1 wherein the second III-nitride layer is In_xGa_1-xN, where 0.05≤

x≤

0.15.

11. The method of claim 2 wherein making at least a portion of the first III-nitride layer porous occurs before forming a mask over the first III-nitride layer.

12. The method of claim 2 wherein making at least a portion of the first III-nitride layer porous occurs after forming a mask over the first III-nitride layer and forming a plurality of openings in the mask.

13. The method of claim 2 wherein growing a second III-nitride layer comprises growing a first portion of the second III-nitride layer under conditions that favor the formation of pyramids of material, then growing a second portion of the second III-nitride layer under conditions that favor lateral growth.

14. The method of claim 1, wherein the n-type region comprises the second III-nitride layer.