Fast settlement of supplement converter for power loss protection system

• US 10,090,675 B1
• Filed: 04/01/2017
• Issued: 10/02/2018
• Est. Priority Date: 06/25/2016
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Lam, Thuc Huu, Trinh, Hue Khac, Watanabe, Hiroshi
• Primary Examiner(s): Benitez, Gustavo Rosario
• Application Number:
  US15/476,977
• Time in Patent Office: 549 Days
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02J 1/12 Parallel operation of dc generators with converters, e.g. with mercury-arc rectifier
• CPC Class Codes: H02J 1/14 Balancing the load in a network
• CPC Class Codes: H02J 7/02 for charging batteries from ac mains by converters
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 5/46 by dynamic converters
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters

Abstract

A power loss protection integrated circuit includes a VIN terminal, a VOUT terminal, an STR terminal, a switch circuit (eFuse), a control circuit, and a prebiasing circuit. In a normal mode, current flows from a power source, into VIN, through the eFuse, out of VOUT, and to the output node. A switching converter of which the control circuit is a part is disabled. If a switch over condition then occurs, the eFuse is turned off and the switching converter starts operating. The switching converter receives energy from STR and drives the output node. Switch over is facilitated by prebiasing. Prior to switch over, the prebiasing circuit prebiases a control loop node as a function of eFuse current flow prior to switch over. When the switching converter begins operating, the node is already prebiased for the proper amount of current to be supplied by the switching converter onto the output node.

Claims

1. An integrated circuit comprising:

a first terminal;

a second terminal;

a current switch circuit that has an on state and an off state, wherein in the on state the current switch circuit provides a low resistance current path from the first terminal, through the current switch circuit, out of the integrated circuit via the second terminal, and to an output node, wherein in the off state the current switch circuit decouples the first terminal from the second terminal, and wherein the current switch circuit outputs a sense current signal indicative of a magnitude of a current flow through the current switch circuit;

a third terminal;

a switching converter control circuit that is a part of a switching converter, wherein the switching converter has a buck on state, wherein the switching converter control circuit is coupled to receive a voltage from the third terminal such that the switching converter in the buck on state drives a regulated voltage onto the output node, wherein the switching converter control circuit has a control loop node, and wherein if the switching converter is not in the buck on state then the switching converter does not drive any regulated voltage onto the output node; and

a prebiasing circuit that receives the sense current signal from the current switch circuit and that is coupled to drive a prebias signal onto the control loop node, wherein the prebiasing circuit is enabled to drive the prebias signal onto the control loop node if the switching converter is not in the buck on state, and wherein the prebiasing circuit is disabled from driving the prebias signal onto the control loop node if the switching converter is in the buck on state.

2. The integrated circuit of claim 1, wherein the sense current signal is a current signal that has a magnitude that is proportional to a magnitude of current flow from the first terminal, through the current switch circuit, and to the second terminal.

3. The integrated circuit of claim 1, wherein the prebias signal that the prebiasing circuit drives onto the control loop node has a magnitude that is a function of a magnitude of current flow from the first terminal, through the current switch circuit, and to the second terminal.

4. The integrated circuit of claim 1, wherein the switching converter comprises the switching converter control circuit as well as additional circuit components that are external to the integrated circuit.

5. The integrated circuit of claim 1, wherein the second terminal is a part of the output node.

6. The integrated circuit of claim 1, wherein the switching converter control circuit has an error amplifier, and wherein the error amplifier is coupled to drive the control loop node when the switching converter is in the buck on state.

7. The integrated circuit of claim 1, wherein the prebias signal is a voltage signal.

8. The integrated circuit of claim 1, further comprising:

a fourth terminal that is coupled to the control loop node.

9. The integrated circuit of claim 1, wherein the switching converter also has a boost on state, and wherein the switching converter in the boost on state outputs a current from the integrated circuit via the third terminal.

10. The integrated circuit of claim 1, wherein the prebiasing circuit is enabled to drive the prebias signal onto the control loop node at a time immediately prior to the switching converter entering the buck on state, and wherein the prebiasing circuit is disabled from driving the control loop node upon the switching converter entering the buck on state.

11. The integrated circuit of claim 1, wherein the third terminal is adapted to be coupled to a capacitor bank.

12. The integrated circuit of claim 1, wherein the third terminal is coupled to a capacitor external to the integrated circuit.

13. A method comprising:

(a) conducting current through a current switch circuit from a first terminal, through the current switch circuit, and out of the second terminal;

(b) operating a prebias circuit so that the prebias circuit supplies a prebias signal onto a control loop node of a switching converter;

(c) detecting a switch over condition;

(d) in response to the detecting of the switch over condition in (c) disabling the prebias circuit so that the prebias circuit no longer supplies the prebias signal onto the control loop node; and

(e) in response to the detecting of the switch over condition in (c) begin operating the switching converter as a buck converter so that the switching converter converts a higher voltage present on a third terminal into a lower voltage that the switching converter supplies onto the second terminal, wherein the switching converter is not operating as a buck converter in (a) through (c), and wherein the first terminal, the second terminal, the third terminal, the current switch circuit, the prebias circuit, and the control loop node are parts of an integrated circuit.

14. The method of claim 13, wherein a first part of the switching converter is disposed on the integrated circuit but a second part of the switching converter is external to the integrated circuit.

15. The method of claim 13, wherein the switch over condition is a fault condition.

16. The method of claim 13, wherein the switch over condition is a command receive condition.

17. The method of claim 13, wherein the switch over condition is an undervoltage condition on the first terminal.

18. The method of claim 13, wherein the switch over condition is taken from the group consisting of:

a command receive condition, an overvoltage condition (VOUT>

VIN) in which a voltage VOUT on the second terminal is more than a predetermined voltage higher than a voltage VIN on the first terminal, an undervoltage condition (UV) on the first terminal, a overcurrent condition (HC) through the current switch circuit from the first terminal to the second terminal, and an overvoltage condition (OV) on the first terminal.

19. An integrated circuit comprising:

a first terminal;

a second terminal;

a current switch circuit that has an on state and an off state, wherein in the on state the current switch circuit provides a low resistance current path from the first terminal, through the current switch circuit, out of the integrated circuit via the second terminal, and to an output node, and wherein in the off state the current switch circuit decouples the first terminal from the second terminal;

a third terminal;

a switching converter control circuit that is a part of a switching converter, wherein the switching converter has a buck on state, wherein the switching converter control circuit is coupled to receive a voltage from the third terminal such that the switching converter in the buck on state drives a regulated lower voltage onto the output node, wherein the switching converter control circuit has a control loop node, wherein if the switching converter is not in the buck on state then the switching converter does not drive any regulated voltage onto the output node, and wherein the current switch circuit is in its off state if the switching converter is in the buck on state; and

a prebiasing circuit that is coupled to drive a prebias signal onto the control loop node, and wherein the prebiasing circuit drives a prebias signal onto the control loop node when the current switch circuit is in its on state, and wherein the prebiasing circuit is disabled from driving any signal onto the control loop node if the switching converter is in the buck on state.

20. The integrated circuit of claim 19, wherein the prebiasing circuit receives a digital logic enable signal, wherein the prebiasing circuit is enabled to drive the prebias signal onto the control loop node if the digital logic enable signal has a first digital logic value, and wherein the prebiasing circuit is disabled from driving any signal onto the control loop node if the digital logic enable signal has a second digital logic value.

21. The integrated circuit of claim 20, further comprising:

a serial bus interface adapted to receive a switch over command from a serial bus and in response to cause the digital logic enable signal to transition digital logic states from the first digital logic value to the second digital logic value.