Methods and systems for high bandwidth communications interface

• US 10,091,035 B2
• Filed: 03/13/2017
• Issued: 10/02/2018
• Est. Priority Date: 04/16/2013
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Fox, John, Holden, Brian, Hormati, Ali, Hunt, Peter, Keay, John D., Shokrollahi, Amin, Simpson, Richard, Singh, Anant, Stewart, Andrew Kevin John, Surace, Giuseppe, Ulrich, Roger
• Primary Examiner(s): Tieu, Janice
• Application Number:
  US15/457,935
• Publication Number:
  US 20170279642A1
• Time in Patent Office: 568 Days
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: H01L 29/76833 Buried channel CCD
• CPC Class Codes: H01L 29/76866 Surface Channel CCD
• CPC Class Codes: H01Q 13/24 constituted by a dielectric or ferromagnetic rod or pipe H01Q13/28 takes precedence
• CPC Class Codes: H01Q 13/28 comprising elements constituting electric discontinuities and spaced in direction of wave propagation, e.g. dielectric elements or conductive elements forming artificial dielectric
• CPC Class Codes: H01R 12/00 Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures printed connections to, or between, printed circuits H05K1/11
• CPC Class Codes: H03M 13/31 combining coding for error detection or correction and efficient use of the spectrum without error detection or correction H03M5/14 , H03M5/145
• CPC Class Codes: H03M 5/04 the pulses having two levels
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4919 : using balanced multilevel codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 27/01 : Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 5/02 : Channels characterised by the type of signal

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Claims

1. A method comprising:

receiving symbols of a codeword of a balanced vector signaling code via wires of a multi-wire bus;

introducing, via a respective signal summation node on each wire of the multi-wire bus, a corresponding correction signal for each wire, the correction signal generated based on a re-encoded symbol of a re-encoded codeword, the re-encoded codeword obtained by re-encoding a previously-decoded codeword;

forming a plurality of output signals using a plurality of multi-input comparators, each output signal formed by a respective multi-input comparator forming a respective weighted combination of the received symbols of the codeword, the respective weighted combination determined by a corresponding vector of an orthogonal matrix;

forming a plurality of output data bits from the plurality of output signals; and

generating a re-encoded codeword based on the plurality of output data bits for use in a set of symbols of a codeword received in a subsequent unit interval.

2. The method of claim 1, wherein the symbols of the codeword of the balanced vector signaling code have symbol values selected from the set {±

1/3, ±

1}.

3. The method of claim 2, wherein the codeword is a permutation of ±

[1, −

1/3, −

1/3, −

1/3].

4. The method of claim 1, wherein the orthogonal matrix is a Hadamard matrix.

5. The method of claim 4, wherein the Hadamard matrix is represented as:

6. The method of claim 1, wherein forming the respective combination comprises:

obtaining a respective first sum of a first selected pair of symbols;

obtaining a respective second sum of a second selected pair of symbols; and

comparing the respective first sum and the respective second sum to obtain the respective output signal.

7. The method of claim 1, wherein the symbols of the re-encoded codeword are digital symbols.

8. The method of claim 1, wherein each correction signal has one of at least four possible values.

9. The method of claim 1, further comprising combining un-rolled decision-feedback equalization (DFE) with the plurality of output signals prior to generating the re-encoded codeword.

10. An apparatus comprising:

a set of summation nodes, each summation node configured to receive a respective symbol of a codeword of a balanced vector signaling code via a respective wire of a multi-wire bus and to responsively introduce a corresponding correction signal into the respective wire, the correction signal representing a re-encoded symbol of a re-encoded codeword, the re-encoded codeword obtained by re-encoding a previously-decoded codeword;

a plurality of multi-input comparators configured to form a plurality of output signals, each multi-input comparator configured to form a respective output signal by forming a respective weighted combination of the received symbols of the codeword, the respective weighted combination determined by a corresponding vector of an orthogonal matrix;

a plurality of slicers configured to receive the plurality of output signals and to responsively generate a plurality of output data bits; and

an encoder configured to generate a re-encoded codeword based on the output data bits for use in a set of symbols of a codeword received in a subsequent unit interval.

11. The apparatus of claim 10, wherein the symbols of the codeword of the balanced vector signaling code have symbol values selected from the set {±

1/3, ±

1}.

12. The apparatus of claim 11, wherein the codeword is a permutation of ±

[1, −

1/3, −

1/3, −

1/3].

13. The apparatus of claim 10, wherein the orthogonal matrix is a Hadamard matrix.

14. The apparatus of claim 13, wherein the Hadamard matrix is represented as:

15. The apparatus of claim 10, wherein the multi-input comparators are configured to:

obtain a respective first sum of a first selected pair of symbols;

obtain a respective second sum of a second selected pair of symbols; and

compare the respective first sum and the respective second sum to obtain the respective output signal.

16. The apparatus of claim 10, wherein the symbols of the re-encoded codeword are digital symbols.

17. The apparatus of claim 10, wherein each correction signal has one of at least four possible values.

18. The apparatus of claim 10, further comprising un-rolled decision-feedback equalization (DFE) circuits configured to perform unrolled DFE on the plurality of output signals prior to generating the re-encoded codeword.