Methods for initializing memory devices

• US 10,095,435 B1
• Filed: 10/20/2015
• Issued: 10/09/2018
• Est. Priority Date: 01/09/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: See, Chin Liang
• Primary Examiner(s): Faal, Baboucarr
• Application Number:
  US14/887,822
• Time in Patent Office: 1,085 Days
• Field of Search: None
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

In one embodiment, a method of operating memory circuitry that is coupled to processing circuitry and memory controller circuitry may include a step to initialize a first portion of the memory circuitry with the memory controller circuitry. The method may also include a step to store startup sequence information onto the first portion of the memory circuitry while the memory controller circuitry initializes a second portion of the memory circuitry with the processing circuitry. The second portion of memory circuitry may be different from the first portion of the memory circuitry.

Claims

1. A method of operating memory circuitry coupled to processing circuitry and direct memory access (DMA) memory controller circuitry, the method comprising:

with the DMA memory controller circuitry, initializing a first portion of the memory circuitry; and

with the processing circuitry, storing startup sequence information onto the first portion of the memory circuitry while the DMA memory controller circuitry initializes a second portion of the memory circuitry that is different from the first portion of the memory circuitry, wherein the memory controller circuitry initializes the second portion of the memory circuitry by transmitting a set of predefined memory initialization signals to the second portion of the memory circuitry.

2. The method as defined in claim 1, wherein initializing the first portion of the memory circuitry comprises:

transmitting a predefined logic signal to each bit of the first portion of the memory circuitry.

3. The method as defined in claim 1, wherein the startup sequence information comprises boot-up information.

4. The method as defined in claim 1, wherein the first portion of the memory circuitry has a size that is larger than a size of the startup sequence information.

5. The method as defined in claim 1, wherein the first portion of the memory circuitry has a first size and the second portion of the memory circuitry has a second size that is larger than the first size.

6. The method as defined in claim 1, further comprising:

with the DMA memory controller circuitry, initializing the second portion of the memory circuitry prior to initializing the first portion of the memory circuitry.

7. The method as defined in claim 1, further comprising:

with the processing circuitry, executing the startup sequence information stored on the first portion of the memory circuitry after the second portion of the memory circuitry has been initialized by the DMA memory controller circuitry.

8. A method of operating a direct memory access (DMA) controller coupled to memory circuitry and processing circuitry, the method comprising:

with the DMA controller, initializing a first portion of the memory circuitry; and

with the DMA controller, initializing a second portion of the memory circuitry that is different from the first portion of the memory circuitry while the first portion of the memory circuitry is being accessed by the processing circuitry, wherein initializing the second portion of the memory circuitry comprises transmitting memory initialization signals to the second portion of the memory circuitry before storing system data at the second portion of the memory circuitry.

9. The method as defined in claim 8, wherein the first portion of the memory circuitry has a first capacity that is less than a second capacity of the second portion of the memory circuitry.

10. The method as defined in claim 8, wherein the processing circuitry comprises a device selected from the group of devices consisting of:

a microprocessor device, a field programmable gate array (FPGA) device, and a system-on-chip (SOC) device.

11. The method as defined in claim 8, wherein initializing the first portion of the memory circuitry comprises transmitting a first logic signal to each bit that forms the first portion of the memory circuitry and wherein initializing the second portion of the memory circuitry comprises transmitting a second logic signal to each bit that forms the second portion of the memory circuitry.

12. The method as defined in claim 11, wherein the first logic signal is selected from the group of logic signals consisting of:

a logic high signal and a logic low signal.

13. The method as defined in claim 8, wherein initializing the second portion of the memory circuitry comprises initializing the second portion of the memory circuitry after the first portion of the memory circuitry has been initialized.

14. The method as defined in claim 8, wherein the memory circuitry has a capacity that is greater than 1 gigabyte.

15. An initializing apparatus, comprising:

a memory device;

direct memory access (DMA) memory controller circuitry that is coupled to the memory device, wherein the DMA memory controller circuitry initializes the memory device in first and second stages; and

a processor circuit that is coupled to the memory device and the DMA memory controller circuitry, wherein the processor circuit transmits a startup sequence to a first portion of the memory device that is initialized during the first stage in parallel with an initialization of the second stage of the memory device that initializes an uninitialized portion of memory in the memory device before storing system data at the uninitialized portion of the memory.

16. The initializing apparatus as defined in claim 15, wherein a capacity of the first portion of the memory device is smaller than a capacity of a second portion of the memory device that is initialized during the second stage.

17. The initializing apparatus as defined in claim 15, wherein the processing circuitry further comprises:

error-correction circuitry that generates error correction information that is to be stored within the memory device.