Self-timed random number generator
First Claim
1. An integrated circuit comprising:
- a plurality of chaotic pattern generators (CGs) arranged in a looping sequence, wherein the plurality of CGs are self-timed digital CGs to generate a random digital value, wherein a first CG of the plurality of CGs is coupled to a second CG of the plurality of CGs that is earlier in the looping sequence and to a third CG of the plurality of CGs that is later in the looping sequence, wherein the first CG comprises an asynchronous digital logic circuit comprising;
a first output;
a first input;
a second input; and
a third input,wherein the first input is coupled to the first output and represents a first state Q1 of the first CG, the second input is coupled to a second output of the second CG and represents a second state Q0 of the second CG, and the third input is coupled to a third output of the third CG and represents a third state Q2 of the third CG,wherein the asynchronous digital logic circuit is to update a next state Q1′
of the first CG using the Q0, Q1, and Q2, andwherein the random digital value is generated based on at least an output of the first CG.
2 Assignments
0 Petitions
Accused Products
Abstract
The embodiments described herein describe a chain of pattern generators organized in a ring topology. Each of the pattern generators in the chain includes asynchronous digital logic and implements an update rule that generates a bidirectional pattern within the chain of pattern generators. The asynchronous digital logic of a first pattern generator in the chain asynchronously updates a next state of the first pattern generator based on at least (a) a current state of the first pattern generator, (b) a second state of a second pattern generator that is before the first pattern generator in the chain, and (c) a third state of a third pattern generator that is after the first pattern generator in the chain.
-
Citations
25 Claims
-
1. An integrated circuit comprising:
-
a plurality of chaotic pattern generators (CGs) arranged in a looping sequence, wherein the plurality of CGs are self-timed digital CGs to generate a random digital value, wherein a first CG of the plurality of CGs is coupled to a second CG of the plurality of CGs that is earlier in the looping sequence and to a third CG of the plurality of CGs that is later in the looping sequence, wherein the first CG comprises an asynchronous digital logic circuit comprising; a first output; a first input; a second input; and a third input, wherein the first input is coupled to the first output and represents a first state Q1 of the first CG, the second input is coupled to a second output of the second CG and represents a second state Q0 of the second CG, and the third input is coupled to a third output of the third CG and represents a third state Q2 of the third CG, wherein the asynchronous digital logic circuit is to update a next state Q1′
of the first CG using the Q0, Q1, and Q2, andwherein the random digital value is generated based on at least an output of the first CG. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A circuit comprising:
-
a plurality of flip-flops (FFs); and a chain of self-timed chaotic pattern generators (CGs) organized in a ring topology, wherein outputs of CGs of the chain are coupled to the plurality of flip-flops, wherein each of the CGs of the chain comprises an internal latch to store a current state, an output coupled to the current state, and asynchronous digital logic, wherein the asynchronous digital logic of a first one of the CGs in the chain is to asynchronously update a next state Q1′
of the first one of the CGs based on the current state Q1, a second state Q0 of a second one of the CGs that is before the first one in the chain, and a third state Q2 of a third one of the CGs that is after the first one in the chain, wherein the plurality of FFs capture a random digital value from at least one of the outputs of the CGs in response to a control signal, wherein randomness of the random digital value is based on chaos and metastability of the internal latches of the CGs. - View Dependent Claims (14, 15, 16, 17, 18)
-
-
19. A method comprising:
-
storing a current state Q1 in an internal latch of a first chaotic pattern generator (CG), wherein the first CG is located in a chain of CGs organized in a ring topology; asynchronously updating, by asynchronous digital logic coupled to the internal latch, a next state Q1 of the first CG based on the current state Q1, a second state Q0 of a second CG that is before the first CG in the chain, and a third state Q2 of a third CG that is after the first CG in the chain, wherein the Q1, Q0, and Q2 are output from the chain of CGs and update asynchronously at individual update rates; and latching, by a plurality of flip-flops (FFs), a random digital value from at least one of the outputs of the chain of CGs in response to a control signal, wherein randomness of the random digital value is based on chaos and metastability of internal latches of the chain of CGs. - View Dependent Claims (20, 21, 22, 23, 24)
-
-
25. A circuit comprising
a chain of self-timed pattern generators organized in a ring topology, wherein each of the self-timed pattern generators in the chain comprises asynchronous digital logic and implements an update rule that generates a bidirectional pattern within the chain of self-timed pattern generators, wherein the asynchronous digital logic of a first self-timed pattern generator in the chain is to asynchronously update a next state of the first self-timed pattern generator based on at least (a) a current state of the first self-timed pattern generator, (b) a second state of a second self-timed pattern generator that is before the first self-timed pattern generator in the chain, and (c) a third state of a third self-timed pattern generator that is after the first self-timed pattern generator in the chain, wherein the chain of self-timed pattern generators outputs a random digital value based at least in part on the current state output from the first self-timed pattern generator.
Specification