Vector multiplication with accumulation in large register space

• US 10,095,516 B2
• Filed: 06/29/2012
• Issued: 10/09/2018
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gueron, Shay, Krasnov, Vlad, Valentine, Robert, Sperber, Zeev, Gradstein, Amit, Rubanovich, Simon
• Primary Examiner(s): Sun, Scott C
• Application Number:
  US13/538,523
• Publication Number:
  US 20140006755A1
• Time in Patent Office: 2,293 Days
• Field of Search: None
• CPC Class Codes: G06F 7/52 Multiplying; Dividing G06F7/483 - G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

Claims

1. An apparatus comprising:

a decoder to decode a single vector multiply add instruction into a decoded single vector multiply add instruction; and

an instruction execution pipeline having a vector functional unit to execute the decoded single vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, wherein X is greater than K to store any carry, and the portion is a first portion when a field of the single vector multiply add instruction is a first value and the portion is a non-overlapping second portion when the field is a second value.

2. The apparatus of claim 1 where X and K are specified in an instruction format of the single vector multiply add instruction.

3. The apparatus of claim 1 wherein said vector functional unit includes respective multiplier instances to multiply said respective K bit elements, each of said multiplier instances being substantially the same as an integer floating point multiplier within another execution unit of said instruction execution pipeline.

4. The apparatus of claim 1 wherein said respective input operand is provided by said X bit accumulator.

5. The apparatus of claim 1 where K=52 and X=64.

6. The apparatus of claim 1 wherein X is a nominal bit width of vector elements processed by said instruction execution pipeline.

7. The apparatus of claim 6 wherein said instruction execution pipeline is coupled to vector registers that provide for vectors composed of X bit elements.

8. The apparatus of claim 7 wherein said accumulator is implemented with one of said vector registers.

9. The apparatus of claim 1 wherein said first portion is an upper half.

10. The apparatus of claim 9 wherein said second non-overlapping portion is a lower half.

11. An apparatus comprising:

a decoder to decode a single vector multiply add instruction into a decoded single vector multiply add instruction; and

an instruction execution pipeline having a vector functional unit to execute the decoded single vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, wherein X is greater than K, and the portion is a first portion when a field of the single vector multiply add instruction is a first value and the portion is a non-overlapping second portion when the field is a second value.

12. The apparatus of claim 11 where X and K are specified in an instruction format of the single vector multiply add instruction.

13. The apparatus of claim 11 wherein said vector functional unit includes respective multiplier instances to multiply said respective K bit elements, each of said multiplier instances being substantially the same as an integer floating point multiplier within another execution unit of said instruction execution pipeline.

14. The apparatus of claim 11 wherein said respective input operand is provided by said X bit accumulator.

15. The apparatus of claim 11 where K=52 and X=64.

16. The apparatus of claim 11 wherein X is a nominal bit width of vector elements processed by said instruction execution pipeline.

17. The apparatus of claim 16 wherein said instruction execution pipeline is coupled to vector registers that provide for vectors composed of X bit elements.

18. The apparatus of claim 17 wherein said accumulator is implemented with one of said vector registers.

19. The apparatus of claim 11 wherein no carry logic circuit is implemented in the execution of the decoded single vector multiply add instruction.

20. The apparatus of claim 11 wherein said first portion is an upper half.

21. The apparatus of claim 20 wherein said non-overlapping second portion is a lower half.