System and memory controller for interruptible memory refresh

• US 10,096,353 B2
• Filed: 11/07/2013
• Issued: 10/09/2018
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Fernandez, Carlos A., Henderson, Joab D., Hovis, William P., Sabrowski, Jeffrey A., Saetow, Anuwat, Sethuraman, Saravanan
• Primary Examiner(s): Rossiter, Sean D
• Assistant Examiner(s): Choi, Charles J
• Application Number:
  US14/074,117
• Publication Number:
  US 20150127898A1
• Time in Patent Office: 1,797 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

Claims

1. A method for refreshing a DRAM performed by a memory controller, the method comprising:

communicating a refresh command, in response to expiration of a refresh timer, to the DRAM, the refresh command configured to initiate an interruptible refresh on the DRAM, the interruptible refresh comprising execution of a plurality of segment refreshes, the execution of each of the plurality of segment refreshes separated by interrupt boundaries, the plurality of segment refreshes comprising a first segment refresh and a second segment refresh, the first segment refresh and the second segment refresh separated by a first interrupt boundary, the DRAM configured to complete the interruptible refresh without additional refresh commands from the memory controller; and

communicating, during execution of the refresh command, a first command to the DRAM before execution of the second segment refresh and after execution of the first segment refresh has begun, the first command configured to cause the DRAM to execute the first command at the first interrupt boundary, the first command further configured to cause the DRAM to delay execution of the second segment refresh until after the first command has been executed.

2. The method of claim 1, wherein the communicating the first command to the DRAM occurs at the first interrupt boundary.

3. The method of claim 1, further comprising:

determining that the first command is a high priority command, wherein the communicating the first command occurs in response to the determining.

4. The method of claim 1, further comprising:

determining a priority level for the first command; and

determining a first priority level for the interruptible refresh, wherein the communicating the first command is based on the priority level of the first command and the first priority level of the interruptible refresh.

5. The method of claim 4, further comprising:

determining a priority for a second command;

determining a second priority for the interruptible refresh; and

determining not to communicate a second command to the DRAM based on the priority for the second command and the second priority for the interruptible refresh and allowing a third segment refresh to execute immediately after a second interrupt boundary.

6. The method of claim 1, further comprising:

determining a priority level for the interruptible refresh;

determining priority levels for one or more commands in a queue; and

determining that the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue, wherein the communicating the refresh command occurs in response to the determining the priority level for the interruptible refresh is higher than the priority level for each of the one or more commands in the queue.

7. The method of claim 1, wherein the communicating the first command to the DRAM occurs during execution of the second segment refresh, the first command configured to cause the DRAM to execute the first command at least partially simultaneously with the second segment refresh.

8. A system for refreshing one or more DRAM modules, the system comprising:

a memory controller, the memory controller configured to;

communicate a refresh command, in response to a refresh timer, to a DRAM; and

communicate a first command to the DRAM after execution of a first segment refresh has begun and before execution of a second segment refresh has begun; and

the DRAM configured to;

initiate an interruptible refresh in response to the communicated refresh command, the interruptible refresh comprising execution of a plurality of segment refreshes, the execution of the plurality of segment refreshes separated by interrupt boundaries, the plurality of segment refreshes comprising the first segment refresh and the second segment refresh, the first segment refresh and the second segment refresh separated by a first interrupt boundary;

execute the first command at the first interrupt boundary after execution of the first segment refresh;

delay execution of the second segment refresh until after the first command has been executed; and

complete the interruptible refresh without additional refresh commands from the memory controller.

9. The system of claim 8, wherein the memory controller is configured to communicate the first command to the DRAM at the first interrupt boundary.

10. The system of claim 8, wherein the memory controller is further configured to:

determine that the first command is a high priority command, wherein the memory controller is configured to communicate the first command based on the determining.

11. The system of claim 8, wherein the memory controller is further configured to:

determine a priority level for the first command; and

determine a first priority level for the interruptible refresh, wherein the communicating the first command is based on the priority level of the first command and the first priority level of the interruptible refresh.

12. The system of claim 11, wherein the memory controller is further configured to:

determine a priority for a second command;

determine a second priority for the interruptible refresh; and

determine not to communicate the second command to the DRAM based on the priority for the second command and the second priority for the interruptible refresh and not delay execution of a third segment refresh at a second interrupt boundary.

13. The system of claim 8, wherein the memory controller is further configured to allow the interruptible refresh to complete before expiration of a refresh interval.

14. The system of claim 8, wherein the memory controller is configured to communicate the first command to the DRAM during execution of the second segment refresh, wherein the DRAM is configured to execute the first command at least partially simultaneously with the second segment refresh.

15. A method for refreshing one or more modules of DRAM, the modules communicatively coupled to one or more memory controllers, the method comprising:

detecting, by a first memory controller, that a DRAM requires a refresh of two or more stored values within the DRAM;

sending, by the first memory controller and based on the detecting, a first command to the DRAM, the first command causing the DRAM to start refresh of the two or more stored values;

sending, by the first memory controller during execution of the refresh command and before completion of the refresh but after start of the refresh by the DRAM, a second command to the DRAM, the second command causing the DRAM to delay refresh of the two or more stored values, the second command causing the DRAM to retrieve information from the two or more stored values; and

receiving, by the first memory controller during execution of the refresh command and before completion of the refresh but after start of the refresh by the DRAM, a response to the second command, the response including the retrieved information from the DRAM.

16. The method of claim 15, wherein the detecting is based on expiration of a refresh timer.

17. The method of claim 15, wherein the DRAM is a singular DRAM module.