Method of operation of non-volatile memory device
First Claim
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1. A memory device comprising:
- a first memory cell;
a second memory cell;
a first bit line connected to the first memory cell;
a second bit line connected to the second memory cell;
a first word line connected to the first memory cell and the second memory cell; and
a control circuit configured to, at a time of writing data to the first memory cell;
apply a first voltage to the second bit line,apply a second voltage, which is lower than the first voltage, to the first bit line,apply a third voltage, which is higher than the first voltage, to the first word line,after the first word line is charged to the third voltage, apply the second voltage to the first word line, andduring a period after the first word line is charged to the third voltage and before the first word line drops to the second voltage, (i) maintain the first voltage on the second bit line, and (ii) apply a fourth voltage, which is higher than the second voltage, to the first bit line.
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Abstract
According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.
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Citations
24 Claims
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1. A memory device comprising:
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a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; and a control circuit configured to, at a time of writing data to the first memory cell; apply a first voltage to the second bit line, apply a second voltage, which is lower than the first voltage, to the first bit line, apply a third voltage, which is higher than the first voltage, to the first word line, after the first word line is charged to the third voltage, apply the second voltage to the first word line, and during a period after the first word line is charged to the third voltage and before the first word line drops to the second voltage, (i) maintain the first voltage on the second bit line, and (ii) apply a fourth voltage, which is higher than the second voltage, to the first bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for controlling a memory device, comprising:
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applying, when writing data to a first memory cell which is connected to a first bit line and a first word line, a first voltage to a second bit line at a first timing; applying a second voltage, which is lower than the first voltage, to the first bit line at the first timing; applying a third voltage, which is higher than the first voltage, to the first word line at a second timing which is later than the first timing; after the first word line is charged to the third voltage, applying the second voltage to the first word line at a third timing which is later than the second timing; and during a period after the first word line is charged to the third voltage and before the first word line drops to the second voltage, (i) maintaining the first voltage on the second bit line, and (ii) applying a fourth voltage, which is higher than the second voltage, to the first bit line. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification