Distributed cascode current source for RRAM set current limitation

• US 10,096,360 B2
• Filed: 09/02/2016
• Issued: 10/09/2018
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Hefei Reliance Memory Limited
• Original Assignee: Hefei Reliance Memory Limited
• Inventors: Bateman, Bruce Lynn
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): DINH, MINH D
• Application Number:
  US15/256,465
• Publication Number:
  US 20170004882A1
• Time in Patent Office: 767 Days
• Field of Search: 365 72, 365148
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Claims

1. An apparatus, comprising:

a memory element of a memory cell of a memory cell array, wherein the memory element is coupled to a source line of the memory cell array through a word line select transistor, and wherein the word line select transistor is selectably coupled to a first transistor of a stack of transistors of an array control circuitry; and

a current limiting device coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cell, wherein the current limiting device is selectably coupled to a second transistor of the stack of transistors of the array control circuitry.

2. The apparatus of claim 1, wherein the array control circuitry is coupled to the memory cell array, the array control circuitry configured to control the constant current mode.

3. The apparatus of claim 1, wherein the source line of the memory cell array runs parallel to a bit line of the memory cell array.

4. The apparatus of claim 1, wherein the source line of the memory cell array runs parallel to a word line of the memory cell array.

5. The apparatus of claim 2, wherein the array control circuitry is configured to simultaneously select, for programming from a high resistance state to a low resistance state, another memory cell of the memory cell array.

6. The apparatus of claim 1, wherein the current limiting device comprises a pull-down transistor biased in saturation.

7. An apparatus, comprising:

a memory element of a memory cell of a memory cell array, wherein the memory element is coupled to a source line of the memory cell array through a word line select transistor;

a current limiting device coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cell, wherein the current limiting device comprises a pull-down transistor biased in saturation; and

an array control circuitry coupled to the memory cell array, wherein the array control circuitry comprises a diode configured stack of transistors, wherein a first transistor of the stack is selectably coupled to a gate of the word line select transistor and a second transistor of the stack is coupled to a gate of the pull-down transistor.

8. The apparatus of claim 7, wherein the diode configured stack of transistors comprises a diode configured stack of differently sized transistors.

9. The apparatus of claim 8, wherein a first size of the word line select transistor is less than a second size of the pull-down transistor.

10. The apparatus of claim 9, wherein a size of the first transistor of the stack corresponds to the first size, and wherein a size of the second transistor of the stack corresponds to the second size being different than the first size.

11. The apparatus of claim 7, wherein the memory element comprises a two terminal device.

12. A method, comprising:

selecting at least one memory cell of a memory array;

biasing a gate of a cell select transistor of the at least one memory cell into saturation via a word line corresponding to the at least one memory cell; and

biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation;

wherein biasing the gate of the cell select transistor comprises biasing the gate of the cell select transistor more than a threshold voltage above the gate of the pull-down transistor.

13. The method of claim 12, further comprising activating a bit line corresponding to the at least one memory cell to switch a memory element of the at least one memory cell from a first resistance state to a second resistance state while the gates are biased into saturation.

14. The method of claim 12, further comprising:

biasing at least one of a bit line or word line corresponding to an unselected memory cell of the memory cell differently than a respective one of the bit line or the word line of the at least one memory cell to cause a memory element of the unselected memory cell to conduct less current than a memory element of the at least one memory cell.

15. The method of claim 14, wherein the memory element of the unselected memory cell conducts no current.

16. An apparatus for operating a memory array, the apparatus comprising:

means for biasing a gate of a cell select transistor of a selected memory cell into saturation via a word line corresponding to the selected memory cell; and

means for biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation.

17. The apparatus of claim 16, further comprising means for activating a bit line corresponding to the selected memory cell to switch a memory element of the selected memory cell.

18. The apparatus of claim 16, wherein the gate of the cell select transistor is biased more than a threshold voltage above the gate of the pull-down transistor.