Power switch circuit for non-volatile memory

• US 10,096,368 B2
• Filed: 05/14/2018
• Issued: 10/09/2018
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Huang, Chih-Yang, Ku, Wei-Ming
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/978,363
• Publication Number:
  US 20180261294A1
• Time in Patent Office: 148 Days
• Field of Search: None
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A non-volatile memory includes a power switch circuit and a non-volatile cell array. The power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. A power terminal of the non-volatile cell is connected with the node z for receiving an output signal.

Claims

1. A non-volatile memory, comprising:

a non-volatile cell array having a power terminal; and

a power switch circuit, including;

a first transistor, wherein a first source/drain terminal of the first transistor receives a first supply voltage, a second source/drain terminal of the first transistor is connected with a node z, a gate terminal of the first transistor receives a second supply voltage, a body terminal of the first transistor is connected with the node z, and an output signal is outputted from the node z;

a second transistor, wherein a first source/drain terminal of the second transistor receives the second supply voltage, a second source/drain terminal of the second transistor is connected with the node z, a gate terminal of the second transistor receives the first supply voltage, and a body terminal of the second transistor is connected with the node z; and

a current source connected between a bias voltage and the node z,

wherein the power terminal of the non-volatile cell array is connected with the node z for receiving the output signal; and

wherein if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output signal, wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output signal, wherein if the first supply voltage is equal to the second supply voltage, the bias voltage is selected as the output signal.

2. The non-volatile memory as claimed in claim 1, wherein the bias voltage is equal to the first supply voltage, or the bias voltage is equal to the second supply voltage.

3. The non-volatile memory as claimed in claim 1, wherein the first transistor and the second transistor are n-type transistors, and the current source is a weak current source.