Metallic interconnects products

• US 10,096,547 B2
• Filed: 02/11/2015
• Issued: 10/09/2018
• Est. Priority Date: 10/02/1999
• Status: Expired due to Fees

• Current Assignee: Uri Cohen
• Original Assignee: Uri Cohen
• Inventors: Cohen, Uri
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US14/619,334
• Publication Number:
  US 20150155239A1
• Time in Patent Office: 1,336 Days
• Field of Search: 257751
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

One embodiment is a semiconductor device including: at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom; at least one barrier layer disposed over the sidewalls and bottom; a first metallic layer disposed over the at least one barrier layer; a second metallic layer disposed over the first metallic layer; and a metallic filling layer disposed over the second metallic layer; wherein: the first metallic layer is continuous over the sidewalls and bottom, has a thickness in a range from about 10 Å to no more than 40 Å over a sidewall of the at least one opening; and the second metallic layer, and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys containing one or more of these metals.

Claims

1. A semiconductor device comprising:

at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom;

at least one barrier layer disposed over the sidewalls and bottom of the at least one opening;

a first metallic layer disposed over the at least one barrier layer;

a second metallic layer disposed over the first metallic layer; and

a metallic filling layer disposed over the second metallic layer;

wherein;

(a) the first metallic layer is selected from a group consisting of Co, Ni, and alloys comprising one or more of these metals, and the first metallic layer has a thickness from about 10 Å

to no more than 40 Å

over a sidewall (at mid-depth) of the at least one opening; and

(b) the combined thickness of the first and the second metallic layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 70 Å

or, when the thickness of the first metallic layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first metallic layer over the sidewall (at mid-depth) to no more than 70 Å

.

2. The semiconductor device of claim 1 wherein the second metallic layer and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys comprising one or more of these metals.

3. The semiconductor device of claim 2 wherein the first metallic layer has a thickness from about 10 Å

to no more than 30 Å

over a sidewall (at mid-depth) of the at least one opening.

4. The semiconductor device of claim 2 wherein the first metallic layer has a thickness from about 20 Å

to no more than 30 Å

over a sidewall (at mid-depth) of the at least one opening.

5. The semiconductor device of claim 2, wherein:

(a) the first metallic layer is selected from a group consisting of Co, and Co alloys;

(b) the second metallic layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys; and

(c) at least one barrier layer is selected from a group consisting of Ta, TaN_X, and alloys comprising one or more of these materials.

6. The semiconductor device of claim 3, wherein:

(a) the first metallic layer is selected from a group consisting of Co, and Co alloys;

(b) the second metallic layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys; and

(c) at least one barrier layer is selected from a group consisting of Ta, TaN_X, and alloys comprising one or more of these materials.

7. The semiconductor device of claim 4, wherein:

(a) the first metallic layer is selected from a group consisting of Co, and Co alloys;

(b) the second metallic layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys; and

(c) at least one barrier layer is selected from a group consisting of Ta, TaN_X, and alloys comprising one or more of these materials.

8. The semiconductor device of claim 6 wherein the combined thickness of the first and the second metallic layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 50 Å

or, when the thickness of the first metallic layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first metallic layer over the sidewall (at mid-depth) to no more than 50 Å

.

9. The semiconductor device of claim 8 wherein the combined thickness of the first and the second metallic layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 40 Å

or, when the thickness of the first metallic layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first metallic layer over the sidewall (at mid-depth) to no more than 40 Å

.

10. A semiconductor device comprising:

at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom;

at least one barrier layer disposed over the sidewalls and bottom of the at least one opening;

a first seed layer disposed over the at least one barrier layer;

a second seed layer disposed over the first seed layer; and

a metallic filling layer disposed over the second seed layer;

wherein;

(a) the first seed layer is selected from a group consisting of Co, Ni, and alloys comprising one or more of these metals, and the first seed layer has a thickness from about 20 Å

to no more than 40 Å

over a sidewall (at mid-depth) of the at least one opening; and

(b) the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 60 Å

.

11. The semiconductor device of claim 10 wherein at least one barrier layer is selected from a group consisting of Ta, TaN_X, and alloys comprising one or more of these materials, and the second seed layer and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys comprising one or more of these metals.

12. The semiconductor device of claim 11 wherein the first seed layer has a thickness from about 20 Å

to no more than 30 Å

over a sidewall (at mid-depth) of the at least one opening.

13. The semiconductor device of claim 11 wherein the first seed layer is selected from a group consisting of Co, and Co alloys, and the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

14. The semiconductor device of claim 12 wherein the first seed is selected from a group consisting of Co, and Co alloys, and the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

15. The semiconductor device of claim 11, wherein the second seed layer is selected from a group consisting of Cu, and Cu alloys.

16. The semiconductor device of claim 12, wherein the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 40 Å

.

17. The semiconductor device of claim 10, wherein the second seed layer, and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

18. A semiconductor device comprising:

at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom;

at least one barrier layer disposed over the sidewalls of the at least one opening;

a first seed layer disposed over the at least one barrier layer;

a second seed layer disposed over the first seed layer; and

a metallic filling layer disposed over the second seed layer;

wherein;

(a) the first seed layer is selected from a group consisting of Co, Ni, and alloys comprising one or more of these metals, and the first seed layer has a thickness from about 10 Å

to no more than 30 Å

over a sidewall (at mid-depth);

(b) the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 80 Å

or, when the thickness of the first seed layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 80 Å

; and

(c) the second seed layer and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys comprising one or more of these metals.

19. The semiconductor device of claim 18 wherein at least one barrier layer is selected from a group consisting of Ta, TaN_X, and alloys comprising one or more of these materials.

20. The semiconductor device of claim 19 wherein the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 60 Å

or, when the thickness of the first seed layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 60 Å

.

21. The semiconductor device of claim 19 wherein the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

22. The semiconductor device of claim 21 wherein the first seed layer is selected from a group consisting of Co, and Co alloys.

23. The semiconductor device of claim 22 wherein the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 40 Å

or, when the thickness of the first seed layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 40 Å

.

24. The semiconductor device of claim 19 wherein the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from 20 Å

to no more than 70 Å

or, when the thickness of the first seed layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 70 Å

.

25. The semiconductor device of claim 24 wherein the first seed layer is selected from a group consisting of Co, and Co alloys.

26. The semiconductor device of claim 19 wherein the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

27. The semiconductor device of claim 19 wherein the thickness of the first seed layer over a sidewall (at mid-depth) is from about 20 Å

to no more than 30 Å

, and the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys.

28. The semiconductor device of claim 25 wherein the at least one metallic barrier comprises TaN_X.

29. The semiconductor device of claim 19 wherein the second seed layer and the metallic filling layer are selected from a group consisting of Cu, and Cu alloys, and the combined thickness of the first and the second seed layers over a sidewall (at mid-depth) is from about 20 Å

to no more than 50 Å

or, when the thickness of the first seed layer over the sidewall (at mid-depth) is larger than 20 Å

, from the thickness of the first seed layer over the sidewall (at mid-depth) to no more than 50 Å

.