Method for fabricating glass substrate package

• US 10,096,565 B2
• Filed: 04/01/2017
• Issued: 10/09/2018
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Ping-Jung Yang
• Original Assignee: Ping-Jung Yang
• Inventors: Yang, Ping-Jung
• Primary Examiner(s): McFadden, Michael P
• Application Number:
  US15/476,999
• Publication Number:
  US 20170207188A1
• Time in Patent Office: 556 Days
• Field of Search: 361762, 1762
• CPC Class Codes: H01G 4/129 containing a glassy phase, e.g. glass ceramic
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05688 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/05788 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32151 the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05B 45/60 : Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
• CPC Class Codes: H05K 1/09 : Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H10K 77/10 : Substrates, e.g. flexible substrates
• CPC Class Codes: Y02E 10/549 : Organic PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Claims

1. A structure comprising:

a first glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said first glass substrate beginning at said first surface and ending at said second surface, wherein a first metal layer is under said second surface connected to one of said metal conductors and a bottom most dielectric layer is under said first metal layer, wherein a first metal bump is under said bottom most dielectric layer, wherein said first metal bump is connected to one of said metal conductors through an opening in said bottom most dielectric layer and said first metal layer, wherein said first metal bump comprises a second metal layer and a third metal layer in said opening and under said bottom most dielectric layer;

a first chip over said first surface and connected to said metal bump through one of said metal conductors and said first metal layer; and

a second glass substrate of an organic light-emitting diodes (OLED) display substrate is directly under said first glass substrate and said first chip, wherein said metal bump is between said first and second glass substrates and contacted to an electrode of said OLED display substrate through a conductive layer, wherein said conductive layer is directly between said first and second glass substrates, and wherein said conductive layer directly contacts with said electrode of said OLED display substrate and said first metal bump.

2. The structure of claim 1, wherein said first metal layer comprises a copper layer.

3. The structure of claim 1, wherein said conductive layer comprises an anisotropic conductive film (ACF) layer.

4. The structure of claim 1, wherein said first chip comprises a central-processing-unit (CPU) chip.

5. The structure of claim 1, wherein said electrode is exposed near said OLED display substrate.

6. The structure of claim 1, wherein said first chip comprises a baseband chip.

7. The structure of claim 1, wherein said first chip comprises a logic chip.

8. The structure of claim 1, wherein said second metal layer is between said first and third metal layers, wherein said third metal layer is thicker than said second metal layer.

9. The structure of claim 1, wherein said metal conductor comprises a copper layer.

10. The structure of claim 1, further comprising a second chip and multiple discrete passive components over said first surface, wherein a first contact point of said second chip is electrically coupled with one of said metal conductors and a second contact point of said discrete passive component is electrically coupled with one of said metal conductors.

11. The structure of claim 1, further comprising a second chip and a third chip over said first surface, wherein said third chip is over said second chip, wherein a through-silicon-via metal layer in said second chip.

12. The structure of claim 1, wherein said first glass substrate comprises a solid glass core has a glass transition temperature between 300°

C. and 900°

C.

13. The structure of claim 1, wherein said metal conductor comprises a first edge and a second edge opposite to and substantially parallel with said first edge.

14. The structure of claim 1, wherein said one of said metal conductors comprise a top end and a bottom end, wherein said top and bottom ends have substantially the same width.

15. The structure of claim 1, wherein said one of said metal conductors comprise a top surface and a bottom surface, wherein said top and bottom surfaces have substantially the same area size.

16. The structure of claim 1, further comprises a fourth metal layer over said first surface connected to one of said metal conductors and said first chip, wherein said fourth metal layer is between one of said metal conductors and said first chip.

17. The structure of claim 16, wherein said fourth metal layer comprises a copper layer.

18. The structure of claim 1, wherein said third metal layer comprises an electroplated layer, wherein said electroplated layer comprises a copper layer.

19. The structure of claim 1, wherein said third metal layer comprises an electroplated layer, wherein said electroplated layer comprises a gold layer.

20. The structure of claim 1, wherein said second metal layer comprises a copper layer, wherein said third metal layer comprises a solder layer, and wherein said second metal layer is between said first and third metal layers.