Thin film transistor, method for manufacturing the same, and semiconductor device

• US 10,096,623 B2
• Filed: 12/28/2017
• Issued: 10/09/2018
• Est. Priority Date: 02/20/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kondo, Toshikazu, Kishida, Hideyuki
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US15/856,685
• Publication Number:
  US 20180190680A1
• Time in Patent Office: 285 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78663 : Amorphous silicon transistors
• CPC Class Codes: H01L 29/78678 : with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/12 : Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Claims

1. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a source electrode over the oxide semiconductor layer;

a drain electrode over the oxide semiconductor layer;

a first layer between the oxide semiconductor layer and the source electrode;

a second layer between the oxide semiconductor layer and the drain electrode; and

a third layer over a channel formation region of the oxide semiconductor layer,

wherein each of the first layer, the second layer, and the third layer is configured to be a buffer layer,

wherein each of the first layer, the second layer, and the third layer is in contact with the oxide semiconductor layer,

wherein the third layer comprises a material which is different from a material of the first layer and a material of the second layer, and

wherein the buffer layer comprises titanium.

3. The semiconductor device according to claim 1,

wherein a thickness of the third layer is larger than a thickness of the first layer, and

wherein the thickness of the third layer is larger than a thickness of the second layer.

4. The semiconductor device according to claim 1,

wherein a thickness of the third layer is smaller than a thickness of the first layer, and

wherein the thickness of the third layer is smaller than a thickness of the second layer.

5. The semiconductor device according to claim 1, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the pixel electrode comprises a region overlapping with a capacitor wiring.

6. The semiconductor device according to claim 1, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the pixel electrode comprises a region overlapping with a capacitor element, and

wherein the capacitor element comprises a region where a capacitor wiring, the gate insulating layer and the source electrode or the drain electrode are overlapped.

7. The semiconductor device according to claim 5,

wherein the capacitor wiring is on a same surface as the gate electrode, and

wherein the capacitor wiring comprises a same material as the gate electrode.

2. A semiconductor device comprising:

a gate electrode;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;

a source electrode over the oxide semiconductor layer;

a drain electrode over the oxide semiconductor layer;

a first layer between the oxide semiconductor layer and the source electrode;

a second layer between the oxide semiconductor layer and the drain electrode; and

a third layer over a channel formation region of the oxide semiconductor layer,

wherein each of the first layer, the second layer, and the third layer is configured to be a buffer layer,

wherein each of the first layer, the second layer, and the third layer is in contact with the oxide semiconductor layer,

wherein the third layer comprises a material which is different from a material of the first layer and a material of the second layer,

wherein the buffer layer comprises titanium,

wherein electrical resistivity of the first layer is less than 10<sup>−

3</sup> (Ω

·

m),

wherein electrical resistivity of the second layer is less than 10<sup>−

3</sup> (Ω

·

m), and

wherein electrical resistivity of the third layer is greater than or equal to 10⁶ (Ω

·

m).

8. The semiconductor device according to claim 2,

wherein a thickness of the third layer is larger than a thickness of the first layer, and

wherein the thickness of the third layer is larger than a thickness of the second layer.

9. The semiconductor device according to claim 2,

wherein a thickness of the third layer is smaller than a thickness of the first layer, and

wherein the thickness of the third layer is smaller than a thickness of the second layer.

10. The semiconductor device according to claim 2, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the pixel electrode comprises a region overlapping with a capacitor wiring.

11. The semiconductor device according to claim 2, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the pixel electrode comprises a region overlapping with a capacitor element, and

wherein the capacitor element comprises a region where a capacitor wiring, the gate insulating layer and the source electrode or the drain electrode are overlapped.

12. The semiconductor device according to claim 10,

wherein the capacitor wiring is on a same surface as the gate electrode, and

wherein the capacitor wiring comprises a same material as the gate electrode.