Semiconductor device and method of fabricating the same

• US 10,096,687 B2
• Filed: 05/11/2017
• Issued: 10/09/2018
• Est. Priority Date: 05/11/2016
• Status: Active Grant

• Current Assignee: Hyundai Mobis Co., Ltd.
• Original Assignee: Hyundai Autron Co., Ltd. (Hyundai Mobis Co., Ltd.)
• Inventors: Kim, Tae Youp, Woo, Hyuk, Kim, Young Joon, Park, Tae Young, Cho, Han Sin, Choi, Yoon Chul
• Primary Examiner(s): Sefer, A.
• Application Number:
  US15/592,489
• Publication Number:
  US 20170330945A1
• Time in Patent Office: 516 Days
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to bc separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type.

Claims

1. A semiconductor device comprising:

a substrate which comprises a first surface and a second surface facing the first surface;

an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type;

a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type;

a gate trench which is formed in the epitaxial layer to be spaced apart from the base region;

a source region which is formed in the base region and has the first conductivity type;

a channel region which is formed in the base region to be spaced apart from the source region and the gate trench, and has the first conductivity type; and

a barrier region which is formed between the source region and the channel region and has the second conductivity type.

2. The semiconductor device of claim 1, wherein the barrier region is formed between the source region and the channel region to contact the source region and the channel region.

3. The semiconductor device of claim 1, wherein the barrier region has the same impurity concentration as the base region.

4. The semiconductor device of claim 1, further comprising:

a gate electrode which comprises a first gate electrode portion formed on an upper surface of the epitaxial layer to overlap the barrier region and the channel region and a second gate electrode portion filling the gate trench.

5. The semiconductor device of claim 4, further comprising a trench bottom doped region which is formed in the epitaxial layer on a bottom surface of the gate trench and has the second conductivity type.

6. The semiconductor device of claim 4, wherein a distance from the second gate electrode portion to the barrier region is greater than a distance from the second gate electrode portion to the channel region.

7. The semiconductor device of claim 4, wherein a distance from the second gate electrode portion to the source region is greater than the distance from the second gate electrode portion to the barrier region.

8. The semiconductor device of claim 1, wherein the source region, the channel region and the barrier region are formed at a surface of the epitaxial layer.

9. The semiconductor device of claim 1, further comprising a drain electrode which is formed on the second surface of the substrate.