Method for manufacturing semiconductor structure with multi spacers

• US 10,096,693 B2
• Filed: 02/14/2018
• Issued: 10/09/2018
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Wang, Chih-Hao, Leung, Ying-Keung
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US15/896,394
• Publication Number:
  US 20180175162A1
• Time in Patent Office: 237 Days
• Field of Search: 438284, 438286, 438249, 438749, 438585, 257401, 257368, 257486
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

forming a fin structure over a substrate;

forming a gate structure across the fin structure;

forming a bottom spacer over a lower part of a sidewall of the gate structure;

forming a dummy spacer layer over an upper part of the sidewall of the gate structure;

removing at least a portion of the dummy spacer layer to form a gap exposing the upper part of the sidewall of the gate structure; and

forming an upper spacer in the gap.

2. The method for manufacturing the semiconductor structure as claimed in claim 1, wherein the upper spacer comprises an air gap formed in a dielectric material.

3. The method for manufacturing the semiconductor structure as claimed in claim 1, wherein the bottom spacer and the dummy spacer layer are made of different materials.

4. The method for manufacturing the semiconductor structure as claimed in claim 1, further comprising:

forming a bottom interlayer dielectric layer over the substrate before the dummy spacer layer is formed,

wherein the dummy spacer layer further extends on a top surface of the bottom interlayer dielectric layer.

5. The method for manufacturing the semiconductor structure as claimed in claim 4, wherein a top surface of the bottom interlayer dielectric layer is at a position that is lower than a top surface of the bottom spacer.

6. The method for manufacturing the semiconductor structure as claimed in claim 4, further comprising:

forming an upper interlayer dielectric layer over the dummy spacer layer,

wherein the upper spacer is located between the upper interlayer dielectric layer and the gate structure.

7. The method for manufacturing a semiconductor structure as claimed in claim 4, wherein the upper spacer does not completely fill in the gap formed by removing at least a portion of the dummy spacer layer, such that a second air gap is formed at an end of the dummy spacer layer extending on the top surface of the bottom interlayer dielectric layer.

8. A method for manufacturing a semiconductor structure, comprising:

forming a fin structure over a substrate;

forming an isolation structure around the fin structure;

forming a gate structure across the fin structure and over the isolation structure;

forming a bottom spacer over a lower part of a sidewall of the gate structure;

forming a dummy spacer layer having a first portion over an upper part of the sidewall of the gate structure and a second portion extending along a top surface of the isolation structure;

forming an interlayer dielectric layer covering the first portion and the second portion of the dummy spacer layer; and

replacing the first portion of the dummy spacer layer with an upper spacer.

9. The method for manufacturing a semiconductor structure as claimed in claim 8, further comprising:

replacing the gate structure with a metal gate structure,

wherein the bottom spacer is located at a lower part of a sidewall of the metal gate structure, and the upper spacer is located at an upper part of the sidewall of the metal gate structure.

10. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein replacing the first portion of the dummy spacer layer with the upper spacer comprises:

removing the first portion of the dummy gate spacer to form a gap between the metal gate structure and the interlayer dielectric layer; and

forming the upper spacer in the gap.

11. The method for manufacturing the semiconductor structure as claimed in claim 8, wherein the upper spacer comprises a first air gap formed in a dielectric material.

12. The method for manufacturing a semiconductor structure as claimed in claim 11, wherein the second portion of the dummy spacer layer and the upper spacer are separated by a second air gap.

13. The method for manufacturing a semiconductor structure as claimed in claim 12, wherein the second air gap exposes a portion of the upper spacer.

14. The method for manufacturing the semiconductor structure as claimed in claim 8, wherein the bottom spacer and the dummy spacer layer are made of different materials.

15. A method for manufacturing a semiconductor structure, comprising:

forming a fin structure over a substrate;

forming an isolation structure around the fin structure;

forming a gate structure across the fin structure;

forming a bottom spacer over a lower part of a sidewall of the gate structure and a bottom interlayer dielectric layer around the bottom spacer;

forming a dummy spacer layer having a first portion over an upper part of the sidewall of the gate structure and a second portion over the bottom interlayer dielectric layer;

forming an upper interlayer dielectric layer over the second portion of the dummy spacer layer; and

replacing the first portion of the dummy spacer layer with an upper spacer.

16. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein the upper spacer comprises a first air gap formed in a dielectric material.

17. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein the upper spacer and the second portion of the dummy spacer layer are separated by a second air gap.

18. The method for manufacturing a semiconductor structure as claimed in claim 17, wherein a bottommost portion of the second air gap is at a position higher than a bottom surface of the gate structure.

19. The method for manufacturing a semiconductor structure as claimed in claim 17, wherein the second air gap exposes a portion of the upper spacer.

20. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein a top surface of the bottom interlayer dielectric layer is lower than a top surface of the bottom spacer.