Efficient power management of UART interface

• US 10,101,797 B2
• Filed: 09/27/2014
• Issued: 10/16/2018
• Est. Priority Date: 09/27/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barak, Amit, Poisner, David I., Elad, Yuval, Liondas, Herbert
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Derose, Volvick
• Application Number:
  US14/499,107
• Publication Number:
  US 20160091959A1
• Time in Patent Office: 1,480 Days
• Field of Search: 713320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to efficient and/or robust link power management of a UART (Universal Asynchronous Receiver/Transmitter) interface are described. In an embodiment, logic causes a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface. The message exchange over the data lines of the UART interface is followed by a modification to one or more flow control signals coupled to the UART interface. Other embodiments are also disclosed.

Claims

1. An apparatus comprising:

logic to cause a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface,

wherein the message exchange over the data lines of the UART interface is to be followed by a modification to one or more flow control signals coupled to the UART interface, wherein one or more subsequent interrupts are to be masked after the link enters into the low power consumption state, wherein the one or more masked subsequent interrupts are to be unmasked at both ends of the link after a wake operation, responsive to an interrupt signal or a CTS (Clear To Send) signal, is enabled.

2. The apparatus of claim 1, wherein the one or more flow control signals are to comprise one of the CTS (Clear To Send) signal or an RTS (Request To Send) signal.

3. The apparatus of claim 1, wherein the data lines of the UART interface are to comprise RXD (Receive Data) and TXD (Transmit Data) lines.

4. The apparatus of claim 1, wherein the link is to couple a device and a host and wherein each side of the link is to wait for a CTS signal of the other side to move to a first logic level before proceeding with entry into the low power consumption state.

5. The apparatus of claim 1, comprising wake event detection logic to remain in an active state during residency of the link in the low power consumption state.

6. The apparatus of claim 1, wherein the link is to couple a device and a host and wherein each side of the link is to couple its CTS signal to wake event detection logic that is to remain in an active state during residency of the link in the low power consumption state.

7. The apparatus of claim 1, wherein exit from the low power consumption state is to be initiated by a modification to one of the one or more control flow signals.

8. The apparatus of claim 7, wherein the link is to couple a device and a host and wherein the modification to one of the one or more control flow signals is to include an assertion of an RTS signal of the UART interface by a waking side of the link.

9. The apparatus of claim 8, wherein the assertion of the RTS signal is to be acknowledged by assertion of a CTS signal of the UART interface by the woken side of the link.

10. The apparatus of claim 9, wherein the acknowledgment of the RTS signal is to be followed by a message exchange over the data lines of the UART interface.

11. The apparatus of claim 1, wherein the link is to comprise a point-to-point link.

12. The apparatus of claim 1, wherein the logic, a processor having one or more processor cores, and memory are on a same integrated device.

13. A method comprising:

causing a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface,

wherein the message exchange over the data lines of the UART interface is followed by a modification to one or more flow control signals coupled to the UART interface, wherein one or more subsequent interrupts are masked after the link enters into the low power consumption state, wherein the one or more masked subsequent interrupts are unmasked at both ends of the link after a wake operation, responsive to an interrupt signal or a CTS (Clear To Send) signal, is enabled.

14. The method of claim 13, wherein the one or more flow control signals comprise one of the CTS (Clear To Send) signal or an RTS (Request To Send) signal.

15. The method of claim 13, wherein the data lines of the UART interface comprise RXD (Receive Data) and TXD (Transmit Data) lines.

16. The method of claim 13, further comprising:

the link coupling a device and a host; and

each side of the link waiting for a CTS signal of the other side to move to a first logic level before proceeding with entry into the low power consumption state.

17. The method of claim 13, further comprising wake event detection logic remaining in an active state during residency of the link in the low power consumption state.

18. The method of claim 13, further comprising:

the link coupling a device and a host; and

each side of the link coupling its CTS signal to wake event detection logic that remains in an active state during residency of the link in the low power consumption state.

19. The method of claim 13, further comprising initiating exit from the low power consumption state by a modification to one of the one or more control flow signals.

20. The method of claim 13, further comprising:

the link coupling a device and a host; and

the modification to one of the one or more control flow signals comprising an assertion of an RTS signal of the UART interface by a waking side of the link.

21. The method of claim 20, further comprising acknowledging the assertion of the RTS signal by assertion of a CTS signal of the UART interface by the woken side of the link.

22. The method of claim 21, further comprising following the acknowledgment of the RTS signal by a message exchange over the data lines of the UART interface.

23. A system comprising:

a display device;

a processor coupled to the display device to cause the display device to display one or more images stored in memory;

logic to cause a link to enter into a low power consumption state in response to a message exchange over data lines of a UART (Universal Asynchronous Receiver/Transmitter) interface,

wherein the message exchange over the data lines of the UART interface is to be followed by a modification to one or more flow control signals coupled to the UART interface, wherein one or more subsequent interrupts are to be masked after the link enters into the low power consumption state, wherein the one or more masked subsequent interrupts are to be unmasked at both ends of the link after a wake operation, responsive to an interrupt signal or a CTS (Clear To Send) signal, is enabled.

24. The system of claim 23, wherein the one or more flow control signals are to comprise one of the CTS (Clear To Send) signal or an RTS (Request To Send) signal.

25. The system of claim 23, wherein the data lines of the UART interface are to comprise RXD (Receive Data) and TXD (Transmit Data) lines.