Apparatus and method for non-serializing split locks

• US 10,102,000 B2
• Filed: 04/01/2016
• Issued: 10/16/2018
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Coleman, James A., Drown, Garrett
• Primary Examiner(s): Giardino, Jr., Mark A
• Application Number:
  US15/089,264
• Publication Number:
  US 20170286115A1
• Time in Patent Office: 928 Days
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.

Claims

1. A processor comprising:

a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution;

a shared cache to be shared by two or more of the plurality of cores;

a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting two cache lines, the split lock comprising a first lock preventing more than one split lock operation being performed at once, and a second lock and third lock for each of the two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state, wherein to initiate the split lock operation, the locking agent is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation upon determining no other split lock operation is present;

at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated;

the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.

2. The processor as in claim 1 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines.

3. The processor as in claim 1 wherein the coherence enforcement engine is to enqueue any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines, the coherence enforcement engine to process the new requests after receiving the indication that the transaction is complete from the locking agent.

4. The processor as in claim 3 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, the coherence enforcement engine is to transmit cache line invalidate commands to caching agents of the other cores.

5. The processor as in claim 4 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory.

6. The processor as in claim 1 wherein the core cache comprises a Level 1 (L1) cache and wherein the shared cache comprises a Level 3 (L3) cache.

7. A method comprising:

initiating a split lock operation in a first core in response to detecting a transaction targeting two cache lines of a cache of the first core, the split lock comprising a first lock preventing more than one split lock operation being performed at once, and a second lock and third lock for each of the two cache lines, wherein to initiate the split lock operation, a locking agent of the first core is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation upon determining no other split lock operation is present;

transmitting a request for the two cache lines to be set to an Exclusive state;

responsively causing any copies of the two cache lines in other cores to be invalidated;

permitting the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state; and

upon completion of the transaction, transmitting an indication that the transaction is complete.

8. The method as in claim 7 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines.

9. The method as in claim 7 further comprising:

enqueuing any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines; and

processing the new requests after receiving the indication that the transaction is complete from the locking agent.

10. The method as in claim 9 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, cache line invalidate commands are transmitted to caching agents of the other cores.

11. The method as in claim 10 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory.

12. The method as in claim 7 wherein the cache of the first core comprises a Level 1 (L1) cache.

13. A system comprising:

a memory to store instructions and data;

a processor to execute the instructions and process the data;

a graphics processor to perform graphics operations in response to graphics instructions;

a network interface to receive and transmit data over a network;

an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;

the processor comprising;

a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution;

a shared cache to be shared by two or more of the plurality of cores;

a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting two cache lines, the split lock comprising a first lock preventing more than one split lock operation being performed at once, and a second lock and third lock for each of the two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state, wherein to initiate the split lock operation, the locking agent is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation upon determining no other split lock operation is present;

at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated;

the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.

14. The system as in claim 13 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines.

15. The system as in claim 13 wherein the coherence enforcement engine is to enqueue any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines, the coherence enforcement engine to process the new requests after receiving the indication that the transaction is complete from the locking agent.

16. The system as in claim 15 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, the coherence enforcement engine is to transmit cache line invalidate commands to caching agents of the other cores.

17. The system as in claim 16 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory.

18. The system as in claim 13 wherein the core cache comprises a Level 1 (L1) cache and wherein the shared cache comprises a Level 3 (L3) cache.