Detecting single event upsets and stuck-at faults in RAM-based data path controllers
First Claim
1. A system, comprising:
- a hardware processor and logic integrated with and/or executable by the hardware processor, the logic being configured to;
receive data comprising a plurality of data elements, each data element comprising one or more bits; and
output bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to an input of a data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length that a predetermined maximum burst size;
a first binary sequence generator comprising a read only memory (ROM) having values stored therein, the first binary sequence generator being configured to create a binary sequence comprising a plurality of bonus bits by retrieving the values stored to the ROM in a random or predetermined pattern to produce the binary sequence to have less than a 0.1% chance of matching any sequence of bits in the data while in the data path, wherein a total length of the binary sequence is equal to or greater than the predetermined maximum burst size; and
the first parity module configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element.
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Accused Products
Abstract
In one embodiment, a method includes receiving data including a plurality of data elements and creating a binary sequence having a plurality of bonus bits using a first binary sequence generator. A total length of the binary sequence is equal to or greater than a predetermined maximum burst size, and the first binary sequence generator is configured to produce the binary sequence to have less than a 0.1% chance of matching any sequence of bits in the data while in a data path. Moreover, the method includes providing a parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element and passing bursts of data that include the plurality of data elements along with a number of parity bits to an input of the data path.
14 Citations
20 Claims
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1. A system, comprising:
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a hardware processor and logic integrated with and/or executable by the hardware processor, the logic being configured to; receive data comprising a plurality of data elements, each data element comprising one or more bits; and output bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to an input of a data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length that a predetermined maximum burst size; a first binary sequence generator comprising a read only memory (ROM) having values stored therein, the first binary sequence generator being configured to create a binary sequence comprising a plurality of bonus bits by retrieving the values stored to the ROM in a random or predetermined pattern to produce the binary sequence to have less than a 0.1% chance of matching any sequence of bits in the data while in the data path, wherein a total length of the binary sequence is equal to or greater than the predetermined maximum burst size; and the first parity module configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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receiving, by a processing circuit, data comprising a plurality of data elements, each data element comprising one or more bits; creating a binary sequence comprising a plurality of bonus bits using a first binary sequence generator by retrieving values stored to a read only memory (ROM) in a random or predetermined pattern, wherein a total length of the binary sequence is equal to or greater than a predetermined maximum burst size, and wherein the first binary sequence generator is configured to produce the binary sequence to have less than a 0.1% chance of matching any sequence of bits in the data while in a data path; using a first parity module to provide a parity calculation prior to passing the plurality of data elements to an input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element; and passing, by the processing circuit, bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements to the input of the data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length that a predetermined maximum burst size. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the embodied program instructions executable by a processor to cause the processor to:
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receive, by the processor, data comprising a plurality of data elements, each data element comprising one or more bits; create, by the processor, a binary sequence comprising a plurality of bonus bits using a first binary sequence generator by retrieving values stored to a read only memory (ROM) in a random or predetermined pattern, a total length of the binary sequence being equal to or greater than a maximum burst size of the data, and wherein the binary sequence is produced to have less than a 0.1% chance of matching any sequence of bits in the data while in a data path; use, by the processor, a first parity module configured to provide a parity calculation prior to passing the plurality of data elements to an input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element; and pass, by the processor, bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements to the input of the data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length that a predetermined maximum burst size. - View Dependent Claims (18, 19, 20)
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Specification