Non-destructive analysis to determine use history of processor

• US 10,102,090 B2
• Filed: 05/16/2016
• Issued: 10/16/2018
• Est. Priority Date: 05/16/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jenkins, Keith A., Linder, Barry P., Ray, Emily A., Robertazzi, Raphael P., Song, Peilin, Stathis, James H., Stawiasz, Kevin G., Stellari, Franco, Weger, Alan J., Yashchin, Emmanuel
• Primary Examiner(s): Guyton, Philip
• Application Number:
  US15/156,136
• Publication Number:
  US 20170329685A1
• Time in Patent Office: 883 Days
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

Claims

1. A method for chip testing, comprising:

ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip;

repeating the non-destructive test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test;

selectively deploying the chip under test for future use or discarding the chip under test to prevent the future use, responsive to the stress history of the chip under test,

wherein the non-destructive test procedure comprises;

ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto;

ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks; and

calculating a sum by summing the plurality of pattern ranks,

wherein the sum calculated by said ascertaining step is designated as the baseline, and the sum calculated by said repeating step is compared to the threshold to determine the stress history of the chip under test.

2. The method of claim 1, wherein each of the plurality of pattern ranks comprises a rank for a current one of the plurality of patterns being ranked, and further comprises a starting pattern and an ending pattern, the starting pattern representing an imaginary pattern having an operating period less than the respective minimum operating period of all of the plurality of patterns, and the ending pattern representing an imaginary pattern having the operating period greater than the respective minimum operating period of all of the plurality of patterns.

3. The method of claim 1, wherein each of the plurality of ranks is specified in a binary format.

4. The method of claim 3, wherein the plurality of ranks comprises more than two ranks.

5. The method of claim 1, wherein said ascertaining step corresponds to a baseline establishing stage and the repeating step corresponds to a testing stage,

wherein, for said baseline establishing phase, all of the plurality of ranks are set to one, and

wherein, for said testing stage, any of the plurality of ranks for a given one of the plurality of patterns that is preceded by a different pattern in the testing stage versus the baseline establishing stage are set to zero.

6. The method of claim 1, wherein the threshold is determined based on threshold selection criteria selected from the group consisting of a total number of the plurality of patterns used in the method, a resolution of a test device in determining the minimum operating period, a similarity between the plurality of patterns, and an acceptable variation between the baseline and the sum calculated by said repeating step.

7. The method of claim 1, wherein said ranking step uses a ranking methodology that varies with a total number of the plurality of patterns used in the method and a sensitivity of the functional chip and the chip under test.

8. The method of claim 1, wherein said ascertaining step corresponds to a baseline establishing stage and the repeating step corresponds to a testing stage, and a ranking methodology used in the baseline establishing stage is different than a ranking methodology used in the testing stage.

9. A non-transitory computer readable storage medium comprising a computer readable program for chip testing, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip; and

repeating the non-destructive test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test;

selectively deploying the chip under test for future use or discarding the chip under test to prevent the future use, responsive to the stress history of the chip under test,

wherein the non-destructive test procedure comprises;

ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto;

ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks; and

calculating a sum by summing the plurality of pattern ranks,

wherein the sum calculated by said ascertaining step is designated as the baseline, and the sum calculated by said repeating step is compared to the threshold to determine the stress history of the chip under test.

10. The non-transitory computer readable storage medium of claim 9, wherein each of the plurality of pattern ranks comprises a rank for a current one of the plurality of patterns being ranked, and further comprises a starting pattern and an ending pattern, the starting pattern representing an imaginary pattern having an operating period less than the respective minimum operating period of all of the plurality of patterns, and the ending pattern representing an imaginary pattern having the operating period greater than the respective minimum operating period of all of the plurality of patterns.

11. The non-transitory computer readable storage medium of claim 9, wherein each of the plurality of ranks is specified in a binary format.

12. The non-transitory computer readable storage medium of claim 11, wherein the plurality of ranks comprises more than two ranks.

13. The non-transitory computer readable storage medium of claim 9, wherein said ascertaining step corresponds to a baseline establishing stage and the repeating step corresponds to a testing stage,

wherein, for said baseline establishing phase, all of the plurality of ranks are set to one, and

wherein, for said testing stage, any of the plurality of ranks for a given one of the plurality of patterns that is preceded by a different pattern in the testing stage versus the baseline establishing stage are set to zero.

14. The non-transitory computer readable storage medium of claim 9, wherein the threshold is determined based on threshold selection criteria selected from the group consisting of a total number of the plurality of patterns used in the method, a resolution of a test device in determining the minimum operating period, a similarity between the plurality of patterns, and an acceptable variation between the baseline and the sum calculated by said repeating step.

15. The non-transitory computer readable storage medium of claim 9, wherein said ranking step uses a ranking methodology that varies with a total number of the plurality of patterns used in the method and a sensitivity of the functional chip and the chip under test.

16. The non-transitory computer readable storage medium of claim 9, wherein said ascertaining step corresponds to a baseline establishing stage and the repeating step corresponds to a testing stage, and a ranking methodology used in the baseline establishing stage is different than a ranking methodology used in the testing stage.

17. A system for chip testing, comprising:

an evaluation processor configured to;

ascertain, in a baseline establishing stage, a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip; and

repeat, in a testing stage, the non-destructive test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test;

selectively deploy the chip under test for future use or discard the chip under test to prevent the future use, responsive to the stress history of the chip under test,

wherein the non-destructive test procedure comprises ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the plurality of pattern ranks, and

wherein the sum calculated in the baseline establishing stage is designated as the baseline, and the sum calculated in the testing stage is compared to the threshold to determine the stress history of the chip under test.

18. The system of claim 17, wherein each of the plurality of ranks is specified in a binary format.

19. The system of claim 18, wherein the plurality of ranks comprises more than two ranks.

20. The system of claim 17, wherein the threshold is determined based on threshold selection criteria selected from the group consisting of a total number of the plurality of patterns used in the method, a resolution of a test device in determining the minimum operating period, a similarity between the plurality of patterns, and an acceptable variation between the baseline and the sum calculated by said repeating step.