Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

• US 10,102,126 B2
• Filed: 06/24/2016
• Issued: 10/16/2018
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Ramanujan, Raj K., Agarwal, Rajat, Hinton, Glenn J.
• Primary Examiner(s): Song, Jasmine
• Application Number:
  US15/192,871
• Publication Number:
  US 20170031821A1
• Time in Patent Office: 844 Days
• Field of Search: 711105
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Claims

1. A multi-level memory system comprising:

a processor having a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy;

a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and

a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory is to maintain its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of a computer system;

a memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller to designate a plurality of different modes of operation for the first level memory including a first mode in which the first-level memory operates as a memory cache for the second-level memory and a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, wherein in the first mode, the first-level memory is organized into different cache regions that provide caching for respective system address ranges.

2. The system as in claim 1 wherein when the memory controller is to designate a plurality of sub-modes when in the first mode of operation, the sub-modes including a write-back caching mode of operation such that a write operation is performed to update the second-level memory only when a cache line within the first-level memory is to be replaced by another cache line.

3. The system as in claim 1 wherein when the memory controller is to designate a plurality of sub-modes when in the first mode of operation, the sub-modes including a first-level memory bypass mode in which all reads and writes go directly to the second-level memory.

4. The system as in claim 1 wherein when the memory controller is to designate a plurality of sub-modes when in the first mode of operation, the sub-modes including a first-level memory read-cache-write mode in which writes go directly to the second-level memory and read caching of persistent data in the first-level memory is permitted.

5. The system as in claim 1 wherein when the memory controller is to designate a plurality of sub-modes when in the first mode of operation, the sub-modes including a first-level memory read-cache write-through mode in which read caching of persistent data in the first-level memory is permitted and write-hits are also cached.

6. The system as in claim 1 wherein the second level memory comprises stacked storage cells.

7. The system as in claim 6 wherein the second level memory comprises any of:

a phase change memory;

resistive memory;

ferroelectric memory;

ferromagnetic memory;

spin transfer torque memory;

spin tunneling memory;

magnetoresistive memory;

a memory comprising storage cells comprised of chalcogenide.

8. The system as in claim 1 wherein the first cache management policy operates independently from a second cache management policy associated with the first mode.

9. A computer system comprising:

a processor having a plurality of cores to execute instructions and process data and one or more processor caches to cache instructions and data according to a first cache management policy;

a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and

a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at a granularity equivalent to a memory subsystem of the computer system;

a memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller configurable to cause the first level memory to operate in a plurality of different modes of operation in which the first-level memory is to operate as a memory cache for the second-level memory in which the first-level memory is organized into different cache regions that provide caching for respective system address ranges, at least one of the modes comprising a write-back caching mode of operation such that a write operation is performed to update the second-level memory only when a cache line within the first-level memory is to be replaced by another cache line.

10. The system as in claim 9 wherein one of the modes comprises a first-level memory bypass mode in which all reads and writes go directly to the second-level memory.

11. The system as in claim 9 wherein one of the modes comprises a first-level memory read-cache-write mode in which writes go directly to the second-level memory and read caching of persistent data in the first-level memory is permitted.

12. The system as in claim 9 wherein one of the modes comprises a first-level memory read-cache write-through mode in which read caching of persistent data in the first-level memory is permitted and write-hits are also cached.

13. The system as in claim 9 wherein one of the first set of characteristics comprises a first power consumption level and the second set of characteristics comprises a second power consumption level which is relatively lower than the first power consumption level.

14. The system as in claim 9 wherein one of the first set of characteristics comprises a first density and the second set of characteristics comprises a second density which is relatively higher than the first density.

15. The system as in claim 9 wherein one of the second set of characteristics comprises the second level memory being directly writable so as to not require erasing of existing data prior to writing.

16. The system as in claim 9 wherein the first level memory comprises a dynamic random access memory (DRAM) and wherein the one or more processor caches comprise static random access memories (SRAMs).

17. The system as in claim 9 wherein the second level memory comprises stacked storage cells.

18. The system as in claim 17 wherein the second level memory comprises any of:

a phase change memory;

resistive memory;

ferroelectric memory;

ferromagnetic memory;

spin transfer torque memory;

spin tunneling memory;

magnetoresistive memory;

a memory comprising storage cells comprised of chalcogenide.

19. An apparatus, comprising:

a memory controller having interface circuitry to interface with

a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and

a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at cache line granularity;

the memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller having a plurality of different modes of operation for the first level memory including a first mode in which the first-level memory is to operate as a memory cache and not a last level cache for the second-level memory and a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space.

20. An apparatus, comprising:

a memory controller having interface circuitry to interface with

a first-level memory having a first set of characteristics associated therewith, the first set of characteristics including a first read access speed and a first write access speed; and

a second-level memory having a second set of characteristics associated therewith, the second set of characteristics including second read and write access speeds at least one of which is relatively lower than either the first read access speed or first write access speed, respectively, non-volatility such that the second level memory maintains its content when power is removed, random access and memory subsystem addressability such that instructions or data stored therein may be accessed at cache line granularity;

the memory controller to receive memory requests and to distribute the memory requests between the first and the second level memories, the memory controller a plurality of different modes of operation for the first level memory including a first mode in which the first-level memory is to operate as a memory cache for the second-level memory and a second mode in which the first-level memory is allocated a first address range of a system address space with the second-level memory being allocated a second address range of the system address space, wherein in the first mode, the first-level memory is organized into different cache regions that provide caching for different respective contiguous system address ranges.