Division of data storage in single-storage device architecture

• US 10,102,138 B2
• Filed: 10/22/2015
• Issued: 10/16/2018
• Est. Priority Date: 10/22/2015
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Lin, Tino
• Primary Examiner(s): Mackall, Larry T
• Application Number:
  US14/920,834
• Publication Number:
  US 20170116131A1
• Time in Patent Office: 1,090 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 9/441 Multiboot arrangements, i.e. selecting an operating system to be loaded

Abstract

Systems and methods are disclosed for sub-dividing data in non-volatile data storage modules. A data storage device includes a non-volatile memory comprising a plurality of physical addresses (PBAs) storing data for a first logical unit number (LUN) and a second LUN, as well as controller circuitry configured to receive a storage access request from a host system, the storage access request including a logical address (LBA), an address range, and LUN identification information. The controller circuitry is further configured to map the LBA to a translated LBA that is one of N contiguous comprehensive LBAs based on the LBA and the LUN identification information, the comprehensive LBAs being associated with both the first LUN and the second LUN, map the translated LBA to one of the plurality of PBAs of the non-volatile memory, and read from or write to at least the one of the plurality of PBAs.

Claims

1. A data storage device comprising:

a non-volatile memory comprising a plurality of physical addresses storing data for a first logical unit number (LUN) and a second LUN;

controller circuitry configured to;

receive a storage access request from a host system, the storage access request including a logical address (LBA), an address range, and LUN identification information;

map the LBA to a translated LBA that is one of N contiguous comprehensive LBAs based on the LBA and the LUN identification information, the comprehensive LBAs being associated with both the first LUN and the second LUN, wherein alternating subsets of M contiguous LBAs of the comprehensive LBAs are associated with the first LUN and the second LUN, respectively;

map the translated LBA to one of the plurality of physical addresses of the non-volatile memory; and

read from or write to at least the one of the plurality of physical addresses by at least;

determining that the address range crosses a boundary of the alternating subsets of LBAs by performing a modulo operation on each of a plurality of LBAs associated with the storage access request and determining that at least one of the modulo operations returns a remainder equal to zero;

generating a first storage access command for accessing a first of the alternating subsets of LBAs associated with the LBA of the storage access request;

generating a second storage access command for accessing a second of the alternating subsets of LBAs; and

providing the first and second storage access commands to additional control circuitry associated with the non-volatile memory using a data storage interface.

2. The data storage device of claim 1, wherein the non-volatile memory comprises magnetic disk memory.

3. The data storage device of claim 1, wherein the controller circuitry is further configured to maintain a first boot record in the first LUN and a second boot record in the second LUN.

4. The data storage device of claim 1, wherein M LBAs corresponds to 1 megabyte (MB) of storage.

5. The data storage device of claim 1, wherein said generating the second storage access command comprises:

identifying a first overlapping LBA within the address range that crosses the boundary of the first of the alternating subsets of LBAs,

wherein the second storage access command includes a first LBA of the second of the alternating subsets of LBAs, data associated with the first overlapping LBA, and a tail address range that comprises a subset of the address range that overlaps the boundary of the first of the alternating subsets of LBAs.

6. The data storage device of claim 1, wherein:

the first LUN has stored thereon a first operating system;

the second LUN has stored thereon a second operating system; and

each of the first and second operating systems may be booted to the host system independently from the other.

7. The data storage device of claim 1, wherein:

the host system is a mobile computing device;

the data storage device is connected to the host system over a USB interface providing a 5volt (V) power supply; and

the non-volatile memory comprises magnetic disk media.

8. The data storage device of claim 1, wherein the non-volatile memory comprises solid-state memory.

9. The data storage device of claim 1, wherein the data storage device is an external storage device connected to the host system over a physical interface port of the host system.

10. The data storage device of claim 1, wherein said mapping comprises adding an offset number of addresses when the LUN identification information indicates that a storage access command is associated with the second LUN.

11. The data storage device of claim 1, wherein the controller circuitry is further configured to manage the first and second LUNs according to a just a bunch of disks (JBOD) scheme.

12. The data storage device of claim 1, wherein the controller circuitry is further configured to allow access to the first LUN to the host system and limit access to the second LUN to host system.

13. A data storage device comprising:

a non-volatile memory comprising a plurality of physical addresses storing data for a first logical unit number (LUN) and a second LUN;

controller circuitry configured to;

receive a storage access request from a host system, the storage access request including a logical address (LBA), an address range, and LUN identification information;

map the LBA to a translated LBA that is one of N contiguous comprehensive LBAs based on the LBA and the LUN identification information, the comprehensive LBAs being associated with both the first LUN and the second LUN;

map the translated LBA to one of the plurality of physical addresses of the non-volatile memory; and

read from or write to at least the one of the plurality of physical addresses;

wherein alternating subsets of M contiguous LBAs of the comprehensive LBAs are associated with the first LUN and the second LUN, respectively, and

wherein when the LUN identification information indicates that the storage access request is associated with the first LUN, said mapping the LBA to the translated LBA (TLBA) is based on a first equation;

TLBA=((LBA/M)×

2M)+(LBA% M),

where ‘

/’

is a quotient operator and ‘

%’

is a modulo operator.

14. The data storage device of claim 13, wherein when the LUN identification information indicates that the storage access request is associated with the second LUN, said mapping the LBA to the TLBA is based on a second equation:

TLBA=((LBA/M)×

2M)+(LBA% M)+M,

where ‘

/’

is a quotient operator and ‘

%’

is a modulo operator.

15. A method of managing data in a data storage device, the method comprising:

maintaining data for a first logical unit number (LUN) and a second LUN in a non-volatile memory comprising a plurality of physical addresses;

receiving a storage access request from a host system, the storage access request including a logical address (LBA), an address range, and LUN identification information;

mapping the LBA to a translated LBA that is one of N contiguous comprehensive LBAs based on the LBA and the LUN identification information, the comprehensive LBAs being associated with both the first LUN and the second LUN;

mapping the translated LBA to one of the plurality of physical addresses of the non-volatile memory; and

accessing at least the one of the plurality of physical address;

wherein alternating subsets of M contiguous LBAs of the comprehensive LBAs are associated with the first LUN and the second LUN, respectively, and

wherein when the LUN identification information indicates that the storage access request is associated with the first LUN, said mapping the LBA to the translated LBA (TLBA) is based on a first equation;

TLBA=((LBA/M)×

2M)+(LBA% M),

where ‘

/’

is a quotient operator and ‘

%’

is a modulo operator.

16. The method of claim 15, wherein said accessing the physical address comprises:

determining that the address range crosses a boundary of the alternating subsets of LBAs;

generating a first storage access command for accessing a first of the alternating subsets of LBAs associated with the LBA of the storage access request;

generating a second storage access command for accessing a second of the alternating subsets of LBAs; and

providing the first and second storage access commands to additional control circuitry associated with the non-volatile memory using a data storage interface.

17. The method of claim 16, wherein said determining that the address range crosses a boundary comprises:

identifying a position of the translated LBA within the first of the alternating sets of LBAs; and

determining that the address range is greater than a range between the position of the translated LBA and a boundary of the first of the alternating sets of LBAs.

18. The method of claim 17, wherein said generating the second storage access command comprises:

identifying a first overlapping LBA within the address range that crosses the boundary of the first of the alternating subsets of LBAs,

wherein the second storage access command includes a first LBA of the second of the alternating subsets of LBAs, data associated with the first overlapping LBA, and a tail address range that comprises a subset of the address range that overlaps the boundary of the first of the alternating subsets of LBAs.

19. The method of claim 15, wherein when the LUN identification information indicates that the storage access request is associated with the second LUN, said mapping the LBA to the TLBA is based on a second equation:

TLBA=((LBA/M)×

2M)+(LBA% M)+M,

where ‘

/’

is a quotient operator and ‘

%’

is a modulo operator.

20. The method of claim 15, further comprising:

booting a first operating system stored in the first LUN without booting a second operating system stored in the second LUN first; and

booting the second operating system without booting the first operating system.