Methods and apparatus for multi-drop digital bus
First Claim
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1. A digital bus architecture within a given bus node of a plurality of bus nodes, comprising:
- a time-division multiplexing (TDM) signaling protocol configured to transmit a clock signal comprising real-time digital data, the clock signal configured to enable multi-drop connectivity for the real-time digital data over a bus interface; and
the bus interface comprising a tri-level signaling scheme, the tri-level signaling scheme being configured to enable the given bus node to provide the clock signal and the real-time digital data to a plurality of other ones of the plurality of bus nodes;
wherein a data value of the real-time digital data at a time slot of the clock signal is indicated by a voltage level of the clock signal at the time slot;
wherein the tri-level signaling scheme is configured to enable a contention-based access to the bus interface;
wherein each of the plurality of bus nodes is configured to communicate with one another to select which of the plurality of bus nodes comprises the given bus node, the selected given bus node being configured to provide the real-time digital data to the plurality of other bus nodes;
wherein the contention-based access comprises a configuration of the plurality of bus nodes, the configuration of the plurality of bus nodes comprising an assignment of a corresponding time slot to each one of the plurality of other bus nodes; and
wherein subsequent to the configuration of the plurality of bus nodes, the given bus node is further configured to provide the real-time digital data to each one of the plurality of other bus nodes in accordance with the corresponding time slot assigned to each one of the plurality of other bus nodes.
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Abstract
Apparatus and methods for digital bus operation. In one embodiment, the digital bus is a bidirectional, time-division multiplexing (TDM) audio bus operation, and a bus technology is described that enables multi-drop (e.g., multiple device, multiple node, etc.) connectivity for real-time audio over a small form factor interface (e.g., as few as two (2) wires). Specifically, an exemplary tri-level signaling scheme provides bidirectional functionality, real-time clock edges, audio data, in a multi-drop topology in one implementation.
83 Citations
18 Claims
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1. A digital bus architecture within a given bus node of a plurality of bus nodes, comprising:
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a time-division multiplexing (TDM) signaling protocol configured to transmit a clock signal comprising real-time digital data, the clock signal configured to enable multi-drop connectivity for the real-time digital data over a bus interface; and the bus interface comprising a tri-level signaling scheme, the tri-level signaling scheme being configured to enable the given bus node to provide the clock signal and the real-time digital data to a plurality of other ones of the plurality of bus nodes; wherein a data value of the real-time digital data at a time slot of the clock signal is indicated by a voltage level of the clock signal at the time slot; wherein the tri-level signaling scheme is configured to enable a contention-based access to the bus interface; wherein each of the plurality of bus nodes is configured to communicate with one another to select which of the plurality of bus nodes comprises the given bus node, the selected given bus node being configured to provide the real-time digital data to the plurality of other bus nodes; wherein the contention-based access comprises a configuration of the plurality of bus nodes, the configuration of the plurality of bus nodes comprising an assignment of a corresponding time slot to each one of the plurality of other bus nodes; and wherein subsequent to the configuration of the plurality of bus nodes, the given bus node is further configured to provide the real-time digital data to each one of the plurality of other bus nodes in accordance with the corresponding time slot assigned to each one of the plurality of other bus nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of operating a digital audio network comprising a plurality of bus nodes, wherein each bus node comprises one or more audio sources and/or one or more audio sinks, the method comprising:
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arbitrating for control of the digital audio network, the arbitrating comprising dynamically determining which of the plurality of bus nodes comprises a central node; receiving audio data to be transmitted to multiple other ones of the plurality of bus nodes of the digital audio network; transmitting, based on the dynamic determining of which of the plurality of bus nodes comprises the central node, the audio data in accordance with time slots assigned to the multiple other ones of the plurality of bus nodes; transmitting a real-time clock signal with edge transitions and logic levels; and causing each edge transition of the real-time clock signal to convey a clock cycle of the received audio data, and causing each logic level of the real-time clock signal associated with the clock cycle to convey the received audio data. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A simplified digital data interface, comprising:
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a two-wire signaling conductor interface; logic configured to implement a time-divided transmission protocol over the conductor interface so as to enable single-ended signaling for the reception of digital audio data; and logic configured to detect a collision between two or more attempts at the reception of the digital audio data, and based on the detected collision, to wait a randomized period of time before allowing another attempt at the reception of the digital audio data; wherein; the digital audio data is transmitted in the form of a clock signal comprising a plurality of clock cycles; the logic is further configured to derive a data value of the digital audio data from a logic level of the clock signal at a respective clock cycle of the plurality of clock signals; and the time-divided transmission protocol is configured to enable transmission of the digital audio data in accordance with time slots assigned to one or more audio sinks, the clock signal being generated based on the assigned time slots. - View Dependent Claims (16, 17, 18)
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Specification