Forwarding signal supply voltage in data transmission system

• US 10,102,885 B2
• Filed: 12/13/2017
• Issued: 10/16/2018
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C., Poulton, John W.
• Primary Examiner(s): Shah, Tanmay
• Application Number:
  US15/841,049
• Publication Number:
  US 20180158491A1
• Time in Patent Office: 307 Days
• Field of Search: 375285
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

Abstract

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Claims

1. An integrated circuit, comprising:

a receiver configured to receive a first signal from another external integrated circuit over a signaling line via a first pin of the integrated circuit, the received first signal having a signal swing dependent on a first signal supply voltage forwarded from the integrated circuit to said external integrated circuit over a supply voltage rail;

a feedback analyzer circuit configured to analyze a characteristic of the received first signal and generate a control signal for adjusting the first signal supply voltage based on the analysis; and

a voltage regulator configured to generate a second signal supply voltage based on the control signal, the second signal supply voltage forwarded to said another integrated circuit over the supply voltage rail via a second pin of the integrated circuit.

2. The integrated circuit of claim 1, wherein the feedback analyzer circuit is further configured to set the signal swing of the first signal supply voltage generated by the voltage regulator to substantially zero during start-up of the integrated circuit;

and

wherein the feedback analyzer circuit is further configured to adjust the control signal to increase signal swings of subsequent signal supply voltages generated by the voltage regulator until a signal integrity of signals received from said another integrated circuit is at a threshold level.

3. The integrated circuit of claim 1, wherein the feedback analyzer circuit is further configured to set the signal swing of the first signal supply voltage generated by the voltage regulator to a magnitude that is greater than a signal swing threshold during start-up of the integrated circuit;

and

wherein the feedback analyzer circuit is further configured to adjust the control signal to decrease signal swings of subsequent signal supply voltages generated by the voltage regulator until a signal integrity of signals received from said another integrated circuit is at a threshold level.

4. The integrated circuit of claim 1, wherein the feedback analyzer is a bit error rate detection circuit and the characteristic of the received signal is a bit error rate of the received signal.

5. The integrated circuit of claim 1, further comprising:

a transmitter configured to transmit a second signal to said another integrated circuit over the signaling line via the first pin, the second signal having a signal swing dependent on the second signal supply voltage forwarded to said another integrated circuit.

6. The integrated circuit of claim 1, wherein the first signal is referenced to a power supply voltage and the first signal swings substantially symmetrically with respect to the power supply voltage.

7. The integrated circuit of claim 6, wherein the power supply voltage is a ground voltage.

9. The method of claim 1, further comprising:

setting the signal swing of the first signal supply voltage to substantially zero during start-up of the integrated circuit; and

adjusting the control signal to increase signal swings of subsequent signal supply voltages generated by the integrated circuit until a signal integrity of signals received from said another integrated circuit is at a threshold level.

10. The method of claim 1, further comprising:

setting the signal swing of the first signal supply voltage to a magnitude that is greater than a signal swing threshold during start-up of the integrated circuit; and

adjusting the control signal to decrease signal swings of subsequent signal supply voltages generated by the integrated circuit until a signal integrity of signals received from said another integrated circuit is at a threshold level.

11. The method of claim 1, further comprising:

transmitting a second signal to said another integrated circuit over the signaling line via the first pin, the second signal having a signal swing dependent on the second signal supply voltage forwarded to said another integrated circuit.

12. The method of claim 1, wherein the first signal is referenced to a power supply voltage and the first signal swings substantially symmetrically with respect to the power supply voltage.

13. The method of claim 12, wherein the power supply voltage is a ground voltage.

8. A method of an integrated circuit comprising:

receiving a first signal from another external integrated circuit over a signaling line via a first pin of the integrated circuit, the received first signal having a signal swing dependent on a first signal supply voltage forwarded from the integrated circuit to said external integrated circuit over a supply voltage rail;

analyzing a characteristic of the received first signal;

generating a control signal for adjusting the first signal supply voltage based on the analysis;

generating a second signal supply voltage based on the control signal and the first signal supply voltage; and

forwarding the second signal supply voltage to said another integrated circuit over the supply voltage rail via a second pin of the integrated circuit.

14. A memory controller, comprising:

a receiver configured to receive a first signal from a memory device over a signaling line via a first pin of the memory controller, the received first signal having a signal swing dependent on a first signal supply voltage forwarded from the memory controller to the memory device over a supply voltage rail;

a feedback analyzer circuit configured to analyze a characteristic of the received first signal and generate a control signal for adjusting the first signal supply voltage based on the analysis; and

a voltage regulator configured to generate a second signal supply voltage based on the control signal, the second signal supply voltage forwarded to the memory device over the supply voltage rail via a second pin of the memory controller.

15. The memory controller of claim 14, wherein the feedback analyzer circuit is further configured to set the signal swing of the first signal supply voltage generated by the voltage regulator to substantially zero during start-up of the memory controller;

and

wherein the feedback analyzer circuit is further configured to adjust the control signal to increase signal swings of subsequent signal supply voltages generated by the voltage regulator until a signal integrity of signals received from the memory device is at a threshold level.

16. The memory controller of claim 14, wherein the feedback analyzer circuit is further configured to set the signal swing of the first signal supply voltage generated by the voltage regulator to a magnitude that is greater than a signal swing threshold during start-up of the memory controller;

and

wherein the feedback analyzer circuit is further configured to adjust the control signal to decrease signal swings of subsequent signal supply voltages generated by the voltage regulator until a signal integrity of signals received from the memory device is at a threshold level.

17. The memory controller of claim 14, wherein the feedback analyzer is a bit error rate detection circuit and the characteristic of the received signal is a bit error rate of the received signal.

18. The memory controller of claim 14, further comprising:

a transmitter configured to transmit a second signal to the memory device over the signaling line via the first pin, the second signal having a signal swing dependent on the second signal supply voltage forwarded to the memory device.

19. The memory controller of claim 14, wherein the first signal is referenced to a power supply voltage and the first signal swings substantially symmetrically with respect to the power supply voltage.

20. The memory controller of claim 19, wherein the power supply voltage is a ground voltage.