Multi-bit-per-cell three-dimensional one-time-programmable memory

• US 10,102,917 B2
• Filed: 04/14/2017
• Issued: 10/16/2018
• Est. Priority Date: 04/14/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Bui, T.
• Assistant Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US15/488,435
• Publication Number:
  US 20170301405A1
• Time in Patent Office: 550 Days
• Field of Search: 365 96, 365 94, 365103, 365104
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2216/12 Reading and writing aspects of erasable programmable read-only memories
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.

Claims

1. A multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB), comprising:

a semiconductor substrate including transistors thereon;

an OTP array stacked above said semiconductor substrate, said OTP array comprising a plurality of OTP cells including a first unprogrammed dummy OTP cell, second and third programmed dummy OTP cells, each of said OTP cells comprising an antifuse layer, wherein said second and third programmed dummy OTP cells have different states;

a first dummy bit line associated with said first unprogrammed dummy OTP cell;

a second dummy bit line associated with said second programmed dummy OTP cell;

a third dummy bit line associated with said third programmed dummy OTP cell;

a plurality of contact vias coupling said OTP cells to said semiconductor substrate;

a differential amplifier with an input disposed on said semiconductor substrate, wherein said input is coupled with said first and second dummy bit lines during a first measurement, and said input is coupled with said second and third dummy bit lines during a second measurement;

wherein said OTP cells have more than two states, the OTP cell in different states being programmed by different programming currents.

2. The 3D-OTP_MB according to claim 1, wherein said OTP cells are programmed by at least two programming currents.

3. The 3D-OTP_MB according to claim 1, wherein said second dummy OTP cell has a larger resistance than said third dummy OTP cell.

4. The 3D-OTP_MB according to claim 1, wherein the programming current of said second dummy OTP cell is smaller than the programming current of said third dummy OTP cell.

5. A multi-bit-per-cell three-dimensional read-only memory (3D-OTP_MB), comprising:

a semiconductor substrate including transistors thereon;

an OTP array stacked above said semiconductor substrate, said OTP array comprising a plurality of OTP cells including a data OTP cell, a plurality of word lines including a data word line, and a plurality of bit lines including a data bit line, each of said OTP cells comprising an antifuse layer;

a dummy word line in parallel with said data word line;

a dummy bit line in parallel with said data bit line;

a first dummy OTP cell formed at the intersection of said dummy word line and said dummy bit line, wherein said first dummy OTP cell is programmed;

a second dummy OTP cell formed at the intersection of said data word line and said dummy bit line, wherein said second dummy OTP cell is unprogrammed;

a plurality of contact vias coupling said OTP cells to said semiconductor substrate;

wherein said OTP cells have N states with N>

2, the OTP cell in different states being programmed by different programming currents.

6. The 3D-OTP_MB according to claim 5, wherein said OTP array comprises 2N−

2 dummy bit lines.

7. The 3D-OTP_MB according to claim 5, wherein said OTP array comprises N dummy bit lines.

8. The 3D-OTP_MB according to claim 5, further comprising a third dummy OTP cell formed at the intersection of said dummy word line and said data bit line, wherein said third dummy OTP cell is unprogrammed.