Switch circuit with controllable phase node ringing

• US 10,103,140 B2
• Filed: 10/14/2016
• Issued: 10/16/2018
• Est. Priority Date: 10/14/2016
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Pan, Ji, Lui, Sik
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US15/294,518
• Publication Number:
  US 20180108652A1
• Time in Patent Office: 732 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (C_rss) and the second MOS transistor is characterized by a second C_rss that is greater than the first C_rss.

Claims

1. A switch circuit having a first terminal, a second terminal and a control terminal, the switch circuit comprising:

a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between the first terminal and the second terminal, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off, wherein the first and second transistors are formed in a common active device area of a common semiconductor substrate,

wherein the first MOS transistor is characterized by a first reverse gate-to-drain capacitance (C_rss) and the second MOS transistor is characterized by a second Crss that is greater than the first C_rss and wherein the first MOS transistor has a first transistor area and the second MOS transistor has a second transistor area, the second transistor area being a fraction of the first transistor area.

2. The switch circuit of claim 1, wherein a transistor area of the second MOS transistor is between 0.1% and 15% of a total area of the common active device area.

3. The switch circuit of claim 1, wherein each of the first MOS transistor and the second MOS transistor comprises one or more trench transistors, each of the one or more trench transistors having a gate terminal formed in a trench in a semiconductor layer on the common semiconductor substrate, a body region formed in the semiconductor layer and a source region formed proximate the trench.

4. The circuit of claim 3, wherein for each trench transistor of the one or more trench transistors of the second MOS transistor includes a trench and gate terminal formed to a greater depth in the semiconductor layer than for the one or more trench transistors of the first MOS transistor.

5. The circuit of claim 3, wherein trenches for each trench transistor of the one or more trench transistors of the first and second MOS transistors are formed to a common depth and a depth of the body region formed in the semiconductor layer is greater for the first MOS transistor than for the second MOS transistor.

6. The circuit of claim 1, wherein the first MOS transistor is a first NMOS transistor and the second MOS transistor is a second NMOS transistor.

7. The switch circuit of claim 6, wherein each of the first NMOS transistor and the second NMOS transistor comprises one or more trench transistors, each of the one or more trench transistors having a gate terminal formed in a trench in an N-type semiconductor layer on the common N-type semiconductor substrate, a P-type body region formed in the semiconductor layer and an N-type source region formed proximate the trench.

8. The switch circuit of claim 6, wherein the switch circuit is a high-side switch of a buck converter.

9. The switch circuit of claim 8, wherein the buck converter includes a low-side switch having an input terminal, a output terminal, and a low-side control terminal, wherein the second terminal is connected to the input terminal.