Fin deformation modulation

• US 10,103,141 B2
• Filed: 02/12/2016
• Issued: 10/16/2018
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Chih-Tang, Huang, Tai-Chun, Lien, Hao-Ming
• Primary Examiner(s): Pizarro, Marcos D
• Assistant Examiner(s): Crite, Antonio
• Application Number:
  US15/042,414
• Publication Number:
  US 20160163700A1
• Time in Patent Office: 977 Days
• Field of Search: 438700, 438692, 438680, 438311, 438296, 438439, 438427, 438424, 257E21006, 257E21014, 257E21027, 257E21058, 257E21077, 257E2117, 257E21227, 257E21229, 257E21244, 257E21267, 257E21304, 257E21311, 257E21546
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a first Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein the first STI region comprises a first dielectric region;

a second STI region extending into the semiconductor substrate, wherein the second STI region comprises;

a second dielectric region, wherein the first dielectric region and the second dielectric region are formed of a same dielectric material; and

a third dielectric region over a bottom portion of the second dielectric region; and

a gate stack comprising a gate dielectric and a gate electrode over the gate dielectric, wherein the gate stack comprises an edge overlapping a portion of the third dielectric region.

2. The integrated circuit structure of claim 1, wherein the first dielectric region, the second dielectric region, and the third dielectric region have top surfaces substantially planar with each other, and no additional dielectric is between the first dielectric region and the gate dielectric.

3. The integrated circuit structure of claim 1, wherein the second dielectric region and the third dielectric region form a distinguishable interface, and the distinguishable interface has a continuously and smoothly curving shape.

4. The integrated circuit structure of claim 1, wherein the second dielectric region and the third dielectric region are formed of different materials.

5. The integrated circuit structure of claim 1 further comprising:

a gate electrode over the gate dielectric, wherein the gate electrode comprises portions overlapping both the first STI region and the second STI region.

6. The integrated circuit structure of claim 1 comprising:

a plurality of semiconductor strips; and

a plurality of STI regions, with neighboring ones of plurality of STI regions contacting opposite sidewalls of same ones of the plurality of semiconductor strips, wherein the first STI region is one of the plurality of STI regions and contacting sidewalls of two of the plurality of semiconductor strips, and the second STI region contacts a sidewall of an outmost one of the plurality of semiconductor strips.

7. The integrated circuit structure of claim 6, wherein the gate dielectric contacts a top surface and sidewalls of each of the plurality of semiconductor strips.

8. The integrated circuit structure of claim 1, wherein the first STI region further comprises a first liner dielectric underlying the first dielectric region, and the second STI region further comprises a second liner dielectric underlying the second dielectric region.

9. The integrated circuit structure of claim 8, wherein the first liner dielectric and the second liner dielectric are formed of a same dielectric material.

10. An integrated circuit structure comprising:

a semiconductor substrate;

a semiconductor strip over a bulk portion of the semiconductor substrate;

a first Shallow Trench Isolation (STI) region contacting a first sidewall of the semiconductor strip, wherein the first STI region comprises;

a first liner dielectric;

a first dielectric region over the first liner dielectric; and

a second dielectric region over the first dielectric region; and

a second STI region contacting a second sidewall of the semiconductor strip, with the first sidewall and the second sidewall being opposite sidewalls of the semiconductor strip, wherein the second STI region comprises;

a second liner dielectric; and

a third dielectric region over and contacting the second liner dielectric; and

a first gate stack comprising a gate dielectric and a gate electrode overlying the gate dielectric, wherein the first gate stack comprises a portion over and in contact with the first dielectric region and a first portion of the second dielectric region, and wherein a second portion of the second dielectric region is un-overlapped by the first gate stack.

11. The integrated circuit structure of claim 10, wherein the second dielectric region and the third dielectric region are formed of a same dielectric material, and top surfaces of the second dielectric region and the third dielectric region are substantially coplanar with each other.

12. The integrated circuit structure of claim 10, wherein the first liner dielectric and the second liner dielectric are formed of a same dielectric material.

13. The integrated circuit structure of claim 10, wherein an entirety of a top surface of the first dielectric region is continuously and smoothly curved, and wherein the all top surfaces of the third dielectric region are coplanar with each other.

14. The integrated circuit structure of claim 10, wherein the first dielectric region further comprises a planar top surface coplanar with a planar top surface of the second dielectric region.

15. The integrated circuit structure of claim 10 further comprising a second gate stack, wherein the first gate stack and the second gate stack extend from opposite sides of the first STI region toward each other, and wherein the second portion of the second dielectric region is overlapped by a space between the first gate stack and the second gate stack.

16. An integrated circuit structure comprising:

a semiconductor substrate;

a first Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein all dielectric layers in the first STI region have a first total count; and

a second STI region extending into the semiconductor substrate, wherein all dielectric layers in the second STI region have a second total count greater than the first total count;

a semiconductor strip comprising;

a first sidewall contacting a sidewall of the first STI region; and

a second sidewall contacting a sidewall of the second STI region;

a semiconductor fin overlapping the semiconductor strip, wherein the semiconductor fin is higher than top surfaces of the first STI region and the second STI region; and

a gate dielectric on sidewalls and a top surface of the semiconductor fin, wherein the gate dielectric continuously extends from the sidewalls of the semiconductor fin to contact all dielectric layers in the second STI region, and the semiconductor fin and the gate dielectric are parts of a Fin Field-Effect Transistor (FinFET).

17. The integrated circuit structure of claim 16, wherein the second STI region has one layer more that the first STI region, and each of layers in the first STI region and each of layers in the second STI region are in contact with the gate dielectric.

18. The integrated circuit structure of claim 16, wherein all dielectric materials in the first STI region also exist in the second STI region, and the second STI region has an additional layer, with the additional layer formed of a material having a composition different from all compositions of all dielectric layers in the first STI region.

19. The integrated circuit structure of claim 16, wherein the first STI region comprises:

a first liner dielectric;

a first dielectric region over the first liner dielectric; and

a second dielectric region over and contacting a bottom portion of the first dielectric region, wherein the second STI region comprises;

a second liner dielectric; and

a third dielectric region over and contacting the second liner dielectric, wherein the integrated circuit structure further comprises;

a gate stack comprising a portion over and in contact with the first dielectric region and a first portion of the second dielectric region, and wherein a second portion of the second dielectric region is un-overlapped by the gate stack.

20. The integrated circuit structure of claim 19, wherein the gate stack comprises an edge overlapping a portion of the third dielectric region.