NAND string utilizing floating body memory cell

• US 10,103,148 B2
• Filed: 06/21/2017
• Issued: 10/16/2018
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/628,931
• Publication Number:
  US 20170294438A1
• Time in Patent Office: 482 Days
• Field of Search: 36518517
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Claims

1. An integrated circuit comprising:

a semiconductor memory array comprising;

a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;

a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and

a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;

wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell, said floating body region having a bottom surface bounded by an insulator layer;

a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer;

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region so that said second region does not contact said insulator layer; and

a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer;

wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;

wherein each said at least one of said plurality of semiconductor memory cells has only one gate;

wherein serial connections between at least two of said semiconductor memory cells are contactless;

wherein said semiconductor memory array comprises at least one of;

at least two of said select gate drain devices connected to a common bit line;

or at least two of said select gate source devices connected to a common source line; and

a control circuit configured to provide electrical signals to at least one of said first, second or third regions.

2. The integrated circuit of claim 1, wherein said semiconductor memory array comprises:

a first set of two or more said strings of semiconductor memory cells connected to said common bit line, wherein said common bit line is a first common bit line; and

at least a second set of two or more said strings of semiconductor memory cells connected to at least a second common bit line;

wherein said first common bit line and said at least a second common bit line are connected to a primary bit line.

3. The integrated circuit of claim 1, wherein said semiconductor memory array comprises:

a first set of two or more said strings of semiconductor memory cells connected to said common source line, wherein said common source line is a first common source line; and

at least a second set of two or more said strings of semiconductor memory cells connected to at least a second common source line;

wherein said first common source line and said at least a second common source line are connected to a primary source line.

4. The integrated circuit of claim 1, wherein said electrical signals have an amplitude or polarity dependent on an operation of said semiconductor memory array.

5. The integrated circuit of claim 1, wherein said control circuit is configured to provide said electrical signals to one of said first or second regions.

6. The integrated circuit of claim 1, wherein said control circuit is configured to provide said electrical signals to said third region.

7. The integrated circuit of claim 1, wherein said control circuit comprises a first control circuit configured to provide said electrical signals to one of said first or second regions, said integrated circuit further comprising a second control circuit configured to provide electrical signals to said third region.

8. The integrated circuit of claim 6, wherein said control circuit comprises a voltage generator circuit.

9. The integrated circuit of claim 8, further comprising a multiplexer electrically connected between said voltage generator circuit and said third region, said multiplexer configured to apply periodic pulses of positive voltage to said third region.

10. The integrated circuit of claim 1, wherein said control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

11. The integrated circuit of claim 1, wherein said control circuit comprises a read circuit connected to one of said first or second region and configured to read a state of said memory cell.

12. The integrated circuit of claim 11, further comprising a reference generator circuit connected to said read circuit.

13. An integrated circuit comprising:

a semiconductor memory array comprising;

a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;

a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and

a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;

wherein at least one of said plurality of semiconductor memory cells each comprises a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell, said floating body region having a bottom surface bounded by an insulator layer;

a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer;

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region so that said second region does not contact said insulator layer; and

a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer;

wherein applying a voltage to said third region results in at least two stable floating body charge levels;

wherein each said at least one of said plurality of semiconductor memory cells has only one gate;

wherein serial connections between at least two of said semiconductor memory cells are contactless;

wherein said semiconductor memory array comprises at least one of;

at least two of said select gate drain devices connected to a common bit line;

or at least two of said select gate source devices connected to a common source line; and

a control circuit configured to provide electrical signals to said third region.

14. The integrated circuit of claim 13, wherein said semiconductor memory array comprises:

a first set of two or more said strings of semiconductor memory cells connected to said common bit line, wherein said common bit line is a first common bit line; and

at least a second set of two or more said strings of semiconductor memory cells connected to at least a second common bit line;

wherein said first common bit line and said at least a second common bit line are connected to a primary bit line.

15. The integrated circuit of claim 13, wherein said semiconductor memory array comprises:

a first set of two or more said strings of semiconductor memory cells connected to said common source line, wherein said common source line is a first common source line; and

at least a second set of two or more said strings of semiconductor memory cells connected to at least a second common source line;

wherein said first common source line and said at least a second common source line are connected to a primary source line.

16. The integrated circuit of claim 13, wherein said electrical signals have an amplitude or polarity dependent on an operation of said semiconductor memory array.

17. The integrated circuit of claim 13, wherein said control circuit comprises a voltage generator circuit.

18. The integrated circuit of claim 17, further comprising a multiplexer electrically connected between said voltage generator circuit and said third region, said multiplexer configured to apply periodic pulses of positive voltage to said third region.

19. The integrated circuit of claim 13, wherein said control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

20. The integrated circuit of claim 13, wherein said semiconductor memory cells are formed in a fin structure.