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Memory device comprising electrically floating body transistor

  • US 10,103,149 B2
  • Filed: 10/30/2017
  • Issued: 10/16/2018
  • Est. Priority Date: 03/09/2013
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

    a first region in electrical contact with said floating body region;

    a second region in electrical contact with said floating body region and spaced apart from said first region;

    insulating regions adjacent to said floating body region;

    a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein;

    said floating body region is bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region, andwherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states.

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