Memory device comprising electrically floating body transistor
First Claim
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1. A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein;
said floating body region is bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region, andwherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states.
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Abstract
A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
284 Citations
18 Claims
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1. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; insulating regions adjacent to said floating body region; a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein; said floating body region is bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region, and wherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each said semiconductor memory cell includes:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; insulating regions adjacent to said floating body region; a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein; said floating body region is bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region, wherein said buried layer region generates impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states; and wherein said buried layer region is located underneath at least two of said memory cells. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each said semiconductor memory cell includes:
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a floating body region configured to be charged to a level indicative of a state of the memory cell, wherein said state is selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; insulating regions adjacent to said floating body region; a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions, wherein; said floating body region is bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region; wherein said buried layer region are located underneath at least two of said memory cells; and when a first memory cell of at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of electrical signals to said buried layer region maintains said first memory cell in said first state and said second memory cell in said second state. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification