Semiconductor die fabrication methods

• US 10,103,254 B2
• Filed: 06/27/2017
• Issued: 10/16/2018
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph
• Primary Examiner(s): Shingleton, Michael
• Application Number:
  US15/634,827
• Publication Number:
  US 20180019329A1
• Time in Patent Office: 476 Days
• Field of Search: None
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Claims

1. A method of fabricating a semiconductor die comprising:

forming a bulk silicon substrate having a high-resistivity portion;

forming a silicon-germanium bipolar transistor on the bulk silicon substrate, the silicon-germanium bipolar transistor configured as a power amplifier, the bulk silicon substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the bulk silicon substrate further including a trench disposed adjacent to the low-resistivity well;

integrating a front-end module on the high-resistivity bulk silicon substrate, the front-end module including the power amplifier, a switch, and a plurality of filters; and

forming a complementary metal oxide semiconductor field-effect transistor device on the bulk silicon substrate.

2. The method of claim 1 further comprising implanting a low-resistivity substrate on a top surface of the substrate and disposing one or more digital circuit devices on the low-resistivity substrate.

3. The method of claim 2 wherein the low-resistivity substrate is implanted so as to at least partially surround a radio frequency element of the front-end module.

4. The method of claim 1 wherein the bulk silicon substrate is grown using a silicon seed.

5. The method of claim 1 wherein the silicon-germanium bipolar transistor conditions or creates electronic signals.

6. The method of claim 1 further comprising forming a low-resistivity epitaxial layer adjacent to a first portion of a top surface of the bulk silicon substrate at least partially above the high-resistivity portion.

7. The method of claim 6 further comprising destroying at least a portion of the low-resistivity layer to restore a high-resistivity characteristic in a selected region of the bulk silicon substrate.

8. The method of claim 7 wherein destroying the at least the portion of the low resistivity layer is performed by treating a surface of the semiconductor die with Argon gas.

9. The method of claim 7 further comprising disposing a passive device above the selected region of the bulk silicon substrate.

10. The method of claim 6 wherein the low-resistivity epitaxial layer includes material from an implanted sub-collector region of the silicon-germanium bipolar transistor that has out-diffused during processing of the silicon-germanium bipolar transistor.

11. The method of claim 1 wherein the low-resistivity well at least partially surrounds the silicon-germanium bipolar transistor.

12. The method of claim 1 wherein the low-resistivity well provides at least partial electrical isolation between the silicon-germanium bipolar transistor and one or more elements of the front-end module.

13. A method of fabricating a semiconductor die comprising:

forming a substrate having a high-resistivity portion;

forming a silicon-germanium bipolar transistor on the substrate, the silicon-germanium bipolar transistor configured as a power amplifier, the substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the substrate further including a trench disposed adjacent to the low-resistivity well;

forming a number of active devices on the substrate, the active devices including the power amplifier, a switch, and a plurality of filters; and

forming at least one additional transistor of a different material than the silicon-germanium bipolar transistor on the substrate.

14. The method of claim 13 wherein the at least one additional transistor is a complementary metal oxide semiconductor field-effect transistor.

15. The method of claim 13 wherein the substrate is a bulk silicon substrate.

16. The method of claim 13 wherein the active devices are part of a front-end module.

17. The method of claim 13 further comprising forming a low-resistivity substrate on a surface of the substrate.

18. The method of claim 17 further comprising treating at least a portion of the low-resistivity substrate with a structure altering substance.

19. The method of claim 18 further comprising disposing a passive device above the portion of the low-resistivity substrate treated with the structure altering substance.

20. The method of claim 13 wherein the low-resistivity well provides at least partial electrical isolation between the silicon-germanium bipolar transistor and the number of active devices.